-------------------------------------------------------------------------------
-- Title      : Bench for Ethernet TX Core
-- Project    : EthMAC
-------------------------------------------------------------------------------
-- File       : bench/bench_ethmac_tx.vhd
-- Author     : Mario Hüttel <mario.huettel@gmx.net>
-- Standard   : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Test bench for TX core.
-------------------------------------------------------------------------------
-- Copyright (c) 2016
--
-- This file is part of EthMAC.
--
-- EthMAC is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 2 of the License.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code.  If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------

library ieee;
library design;

use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use design.all;

entity bench_ethmac_tx is
end entity bench_ethmac_tx;

architecture RTL of bench_ethmac_tx is
	signal clk            : std_logic;
	signal rst            : std_logic;
	signal tx_ready       : std_logic;
	signal start_of_frame : std_logic;
	signal end_of_frame   : std_logic;
	signal data_in        : std_logic_vector(7 downto 0);
	signal data_ack       : std_logic;
	signal abort          : std_logic;
	signal rmii_tx        : std_logic_vector(1 downto 0);
	signal rmii_txen      : std_logic;

begin
	clock_driver : process
		constant period : time := 20 ns;
	begin
		clk <= '0';
		wait for period / 2;
		clk <= '1';
		wait for period / 2;
	end process clock_driver;

	ethmac_tx_inst : entity design.ethmac_tx
		port map(
			clk_50         => clk,
			rst            => rst,
			tx_ready       => tx_ready,
			start_of_frame => start_of_frame,
			end_of_frame   => end_of_frame,
			data_in        => data_in,
			data_ack       => data_ack,
			abort          => abort,
			rmii_tx        => rmii_tx,
			rmii_txen      => rmii_txen
		);


	abort <= '0';
	
	sendpkg : process is
		procedure sendByte(byte : std_logic_vector(7 downto 0); last : std_logic) is
		begin
			wait until rising_edge(clk);
			data_in      <= byte;
			end_of_frame <= last;
			wait until data_ack = '1';

		end procedure sendByte;

	begin
		rst <= '1';
		wait for 5 ns;
		rst <= '0';
		wait for 20 ns;
		start_of_frame <= '1';
		sendByte(x"FF", '0');
		start_of_frame <= '0';
		sendByte(x"DE", '0');
		sendByte(x"AD", '0');
		sendByte(x"BE", '0');
		sendByte(x"EF", '0');
		sendByte(x"00", '0');

		sendByte(x"01", '0');
		sendByte(x"02", '0');
		sendByte(x"03", '0');
		sendByte(x"04", '0');
		sendByte(x"05", '0');
		sendByte(x"06", '0');

		sendByte(x"01", '0');
		sendByte(x"02", '0');

		sendByte(x"AA", '0');

		sendByte(x"01", '0');
		sendByte(x"02", '0');
		sendByte(x"03", '1');
		
		wait;

	end process sendpkg;

end architecture RTL;