library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity wb2avalon is
	generic (
		ADDR_WIDTH_G : natural := 32;
		DATA_WIDTH_G : natural := 32
	);
	port(
		-- Avalon Signals
		avalon_write       : out std_logic;
		avalon_read        : out std_logic;
		avalon_cs          : out std_logic;
		avalon_waitrequest : in  std_logic;
		avalon_data_in     : in  std_logic_vector(DATA_WIDTH_G-1 downto 0);
		avalon_data_out    : out std_logic_vector(DATA_WIDTH_G-1 downto 0);
		avalon_address     : out std_logic_vector(ADDR_WIDTH_G-1 downto 0);
		-- avalon_response    :  std_logic_vector(1 downto 0);
		-- Wishbone Signals
		wb_cyc             : in  std_logic;
		wb_we              : in  std_logic;
		wb_stb             : in  std_logic;
		wb_ack             : out std_logic;
		wb_address         : in  std_logic_vector(ADDR_WIDTH_G-1 downto 0);
		wb_data_out        : out std_logic_vector(DATA_WIDTH_G-1 downto 0);
		wb_data_in         : in  std_logic_vector(DATA_WIDTH_G-1 downto 0);
		wb_err             : out std_logic;
		wb_rty             : out std_logic
	);
end entity wb2avalon;

architecture RTL of wb2avalon is
begin
	avalon_address <= wb_address;
	avalon_data_out <= wb_data_in;
	wb_data_out <= avalon_data_in;
	
	avalon_cs <= wb_stb;
	avalon_write <= wb_cyc and wb_we;
	avalon_read <= wb_cyc and (not wb_we);
	
	wb_ack <= not avalon_waitrequest;
	
	wb_err <= '0';
	wb_rty <= '0';
	
end architecture RTL;