library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity avalon2wb is
		generic (
		ADDR_WIDTH_G : natural := 32;
		DATA_WIDTH_G : natural := 32
	);
	port(
		-- Avalon Signals
		avalon_write       : in  std_logic;
		avalon_read        : in  std_logic;
		avalon_cs          : in  std_logic;
		avalon_waitrequest : out std_logic;
		avalon_data_in     : in  std_logic_vector(DATA_WIDTH_G-1 downto 0);
		avalon_data_out    : out std_logic_vector(DATA_WIDTH_G-1 downto 0);
		avalon_address     : in  std_logic_vector(ADDR_WIDTH_G-1 downto 0);
		avalon_response    : out std_logic_vector(1 downto 0);
		-- Wishbone Signals
		wb_cyc             : out std_logic;
		wb_we              : out std_logic;
		wb_stb			   : out std_logic;
		wb_ack             : in  std_logic;
		wb_address         : out std_logic_vector(ADDR_WIDTH_G-1 downto 0);
		wb_data_out        : out std_logic_vector(DATA_WIDTH_G-1 downto 0);
		wb_data_in         : in  std_logic_vector(DATA_WIDTH_G-1 downto 0);
		wb_err_i           : in  std_logic;
		wb_rty_i           : in  std_logic
	);
end entity avalon2wb;

architecture RTL of avalon2wb is
	constant RESP_OKAY : std_logic_vector(1 downto 0) := "00";
	constant RESP_SLV_ERR : std_logic_vector(1 downto 0) := "10";
begin
	wb_address <= avalon_address;
	wb_data_out <= avalon_data_in;
	avalon_data_out <= wb_data_in;
	
	wb_cyc <= avalon_write or avalon_read;
	wb_stb <= avalon_cs;
	wb_we <= avalon_write and (not avalon_read);
	
	
	wait_gen : process(wb_ack, wb_rty_i, wb_err_i) is
	begin
		avalon_waitrequest <= '1';
		avalon_response <= RESP_OKAY;
		if wb_ack = '1' then
			avalon_waitrequest <= '0';
		elsif (wb_err_i = '1') or (wb_rty_i = '1') then
			avalon_waitrequest <= '0';
			avalon_response <= RESP_SLV_ERR;	
		end if;
	end process wait_gen;
	
end architecture RTL;