From 212cbcac26168daca95da6a3e1324a528de1737e Mon Sep 17 00:00:00 2001 From: Shino Amakusa Date: Sun, 21 Aug 2016 17:52:29 +0200 Subject: [PATCH] added address and mask arrays to aw rounter. aw router started --- src/axi3-interconnect-aw-router.vhd | 51 +++++++++++++++++++++++-- src/axi3-interconnect-aw-router_pkg.vhd | 2 +- src/axi3-interconnect.vhd | 11 ++++-- src/axi3-interconnect_pkg.vhd | 6 ++- 4 files changed, 60 insertions(+), 10 deletions(-) diff --git a/src/axi3-interconnect-aw-router.vhd b/src/axi3-interconnect-aw-router.vhd index 353ef96..211152f 100644 --- a/src/axi3-interconnect-aw-router.vhd +++ b/src/axi3-interconnect-aw-router.vhd @@ -11,13 +11,56 @@ entity axi3intercon_aw_router is rst : in std_logic; masters_out : in axi_aw_masters_out_t(0 to MASTER_COUNT - 1); masters_in : out axi_aw_masters_in_t(0 to MASTER_COUNT - 1); - slaves_out : in axi_aw_slaves_out_t(0 to SLAVE_COUNT - 1); - slaves_in : out axi_aw_slaves_in_t(0 to SLAVE_COUNT - 1); - write_locks : out write_locks_t(0 to MASTER_COUNT - 1); - write_releases : in write_release_t + slaves_out : in axi_aw_slaves_out_t(0 to SLAVE_COUNT); + slaves_in : out axi_aw_slaves_in_t(0 to SLAVE_COUNT); + write_locks : out write_locks_t(0 to MASTER_COUNT - 1); -- write_* signals come/go from/to the write router. + write_releases : in write_release_t; + address_array : in axi_slave_addresses_t(0 to SLAVE_COUNT - 1); + mask_array : in axi_slave_addresses_t(0 to SLAVE_COUNT - 1) ); end entity axi3intercon_aw_router; architecture RTL of axi3intercon_aw_router is + alias clk is aclk; + type aw_state_t is (READY, ACTIVE, BLK); + type aw_states_t is array (0 to MASTER_COUNT - 1) of aw_state_t; + signal aw_states : aw_states_t; begin + aw_router : process(clk, rst) is + variable slave_block : std_logic_vector(0 to SLAVE_COUNT - 1) := (others => '0'); + variable slave_idx : integer range 0 to SLAVE_COUNT := SLAVE_COUNT; -- 1 more slave than connected for handling bad requests. + + procedure calculate_slave(address : in std_logic_vector(ADDRESS_BITS - 1 downto 0)) is + begin + slave_idx := SLAVE_COUNT; + for i in 0 to SLAVE_COUNT - 1 loop + if (address and mask_array(i)) = address_array(i) then + slave_idx := i; + end if; + end loop; + + end procedure calculate_slave; + + begin + if rst = '1' then + for i in 0 to MASTER_COUNT - 1 loop + aw_states(i) <= READY; + end loop; + slave_block := (others => '0'); + elsif rising_edge(clk) then + for i in MASTER_COUNT - 1 downto 0 loop -- Loop for every master + case aw_states(i) is + when READY => + if masters_out(i).awvalid = '1' then + calculate_slave(masters_out(i).awaddr); + -- TODO: Write router itself + -- TODO: lock output + end if; + when others => null; + end case; + + end loop; + end if; + end process aw_router; + end architecture RTL; diff --git a/src/axi3-interconnect-aw-router_pkg.vhd b/src/axi3-interconnect-aw-router_pkg.vhd index 3a5f0fc..eadaaad 100644 --- a/src/axi3-interconnect-aw-router_pkg.vhd +++ b/src/axi3-interconnect-aw-router_pkg.vhd @@ -11,7 +11,7 @@ package axi_aw_router_pkg is type write_lock_t is record locked : std_logic; - slave_idx : integer range 0 to SLAVE_COUNT - 1; + slave_idx : integer range 0 to SLAVE_COUNT; end record write_lock_t; type write_locks_t is array (natural range <>) of write_lock_t; diff --git a/src/axi3-interconnect.vhd b/src/axi3-interconnect.vhd index d88a817..136c5ef 100644 --- a/src/axi3-interconnect.vhd +++ b/src/axi3-interconnect.vhd @@ -17,13 +17,16 @@ entity axi3intercon is end entity axi3intercon; architecture RTL of axi3intercon is + signal address_array : axi_slave_addresses_t(0 to SLAVE_COUNT - 1); + signal mask_array : axi_slave_addresses_t(0 to SLAVE_COUNT - 1); signal rst : std_logic; signal write_locks : write_locks_t(0 to MASTER_COUNT - 1); signal write_releases : write_release_t; signal aw_masters_out : axi_aw_masters_out_t(0 to MASTER_COUNT - 1); signal aw_masters_in : axi_aw_masters_in_t(0 to MASTER_COUNT - 1); - signal aw_slaves_out : axi_aw_slaves_out_t(0 to SLAVE_COUNT - 1); - signal aw_slaves_in : axi_aw_slaves_in_t(0 to SLAVE_COUNT - 1); + signal aw_slaves_out : axi_aw_slaves_out_t(0 to SLAVE_COUNT); + signal aw_slaves_in : axi_aw_slaves_in_t(0 to SLAVE_COUNT); + begin reset_sync : process(aclk, aresetn) is begin @@ -43,7 +46,9 @@ begin slaves_out => aw_slaves_out, slaves_in => aw_slaves_in, write_locks => write_locks, - write_releases => write_releases + write_releases => write_releases, + address_array => address_array, + mask_array => mask_array ); aw_master_connect : for i in 0 to MASTER_COUNT - 1 generate diff --git a/src/axi3-interconnect_pkg.vhd b/src/axi3-interconnect_pkg.vhd index 5bfef05..dbe2fbc 100644 --- a/src/axi3-interconnect_pkg.vhd +++ b/src/axi3-interconnect_pkg.vhd @@ -210,13 +210,15 @@ package axi3intercon_pkg is b : slave_b_out_t; end record axi_slave_out_t; - -- Array definitions - + -- Connection array definitions type axi_masters_in_t is array (natural range <>) of axi_master_in_t; type axi_masters_out_t is array (natural range <>) of axi_master_out_t; type axi_slaves_in_t is array (natural range <>) of axi_slave_in_t; type axi_slaves_out_t is array (natural range <>) of axi_slave_out_t; + -- Address translation mapping + type axi_slave_addresses_t is array (natural range <>) of std_logic_vector(ADDRESS_BITS - 1 downto 0); + end package axi3intercon_pkg; -- package body axi3intercon_pkg is