diff --git a/src/axi3-interconnect-decerr.vhd b/src/axi3-interconnect-decerr.vhd
index e4b958b..113cbb2 100644
--- a/src/axi3-interconnect-decerr.vhd
+++ b/src/axi3-interconnect-decerr.vhd
@@ -23,6 +23,7 @@ begin
 	read_error : process(clk, rst) is
 	begin
 		if rst = '1' then
+			r_state              <= R_READY;
 			slave_out.ar.arready <= '0';
 			slave_out.r.rdata    <= (others => '0');
 			slave_out.r.rid      <= (others => '0');
@@ -35,11 +36,10 @@ begin
 				when R_READY =>
 					slave_out.r.rlast <= '0';
 					if slave_in.ar.arvalid = '1' then
-						slave_out.ar.arready <= '1';
-						r_state              <= R_ERROR;
-						slave_out.r.rid      <= slave_in.ar.arid;
-						slave_out.r.rresp    <= AXI_RESP_DECERR;
-						slave_out.r.rvalid   <= '1';
+						r_state            <= R_ERROR;
+						slave_out.r.rid    <= slave_in.ar.arid;
+						slave_out.r.rresp  <= AXI_RESP_DECERR;
+						slave_out.r.rvalid <= '1';
 						if unsigned(slave_in.ar.arlen) = 1 then
 							slave_out.r.rlast <= '1';
 						else
@@ -48,8 +48,7 @@ begin
 						r_len <= unsigned(slave_in.ar.arlen);
 					end if;
 				when R_ERROR =>
-					slave_out.ar.arready <= '0';
-					slave_out.r.rvalid   <= '1';
+					slave_out.r.rvalid <= '1';
 					if slave_in.r.rready = '1' then
 						r_len <= r_len - 1;
 						if r_len = 2 then
@@ -64,13 +63,15 @@ begin
 		end if;
 	end process read_error;
 
+	slave_out.ar.arready <= '1' when r_state = R_READY else '0';
+
 	-- AW Acceptor:
 	slave_out.aw.awready <= '1';        -- Always accept write transactions (interconnect will manage that only one is active)
 
 	write_error : process(clk, rst) is
 	begin
 		if rst = '1' then
-			slave_out.w.wready <= '0';
+			w_state            <= W_READY;
 			slave_out.b.bid    <= (others => '0');
 			slave_out.b.bresp  <= (others => '0');
 			slave_out.b.buser  <= (others => '0');
@@ -79,14 +80,12 @@ begin
 			case w_state is
 				when W_READY =>
 					if slave_in.w.wvalid = '1' then
-						slave_out.w.wready <= '1';
 						w_state            <= W_ERROR;
 						slave_out.b.bid    <= slave_in.w.wid;
 						slave_out.b.bresp  <= AXI_RESP_DECERR;
 						slave_out.b.bvalid <= '1';
 					end if;
 				when W_ERROR =>
-					slave_out.w.wready <= '0';
 					if slave_in.b.bready = '1' then
 						slave_out.b.bvalid <= '0';
 						w_state            <= W_READY;
@@ -95,4 +94,6 @@ begin
 		end if;
 	end process write_error;
 
+	slave_out.w.wready <= '1' when w_state = W_READY else '0';
+
 end architecture RTL;