diff --git a/src/axi3-interconnect.vhd b/src/axi3-interconnect.vhd
index b31dea3..ffc6f15 100644
--- a/src/axi3-interconnect.vhd
+++ b/src/axi3-interconnect.vhd
@@ -8,18 +8,18 @@ use work.axi_ar_router_pkg.all;
 
 entity axi3intercon is
 	port(
-		aclk        : in  std_logic;
-		aresetn     : in  std_logic;
-		masters_in  : out axi_masters_in_t(0 to MASTER_COUNT - 1);
-		masters_out : in  axi_masters_out_t(0 to MASTER_COUNT - 1);
-		slaves_in   : out axi_slaves_in_t(0 to SLAVE_COUNT - 1);
-		slaves_out  : in  axi_slaves_out_t(0 to SLAVE_COUNT - 1)
+		aclk          : in  std_logic;
+		aresetn       : in  std_logic;
+		masters_in    : out axi_masters_in_t(0 to MASTER_COUNT - 1);
+		masters_out   : in  axi_masters_out_t(0 to MASTER_COUNT - 1);
+		slaves_in     : out axi_slaves_in_t(0 to SLAVE_COUNT - 1);
+		slaves_out    : in  axi_slaves_out_t(0 to SLAVE_COUNT - 1);
+		address_array : axi_slave_addresses_t(0 to SLAVE_COUNT - 1);
+		mask_array    : axi_slave_addresses_t(0 to SLAVE_COUNT - 1)
 	);
 end entity axi3intercon;
 
 architecture RTL of axi3intercon is
-	signal address_array  : axi_slave_addresses_t(0 to SLAVE_COUNT - 1);
-	signal mask_array     : axi_slave_addresses_t(0 to SLAVE_COUNT - 1);
 	signal rst            : std_logic;
 	signal write_locks    : write_locks_t(0 to MASTER_COUNT - 1);
 	signal write_releases : write_release_t;
@@ -27,6 +27,10 @@ architecture RTL of axi3intercon is
 	signal aw_masters_in  : axi_aw_masters_in_t(0 to MASTER_COUNT - 1);
 	signal aw_slaves_out  : axi_aw_slaves_out_t(0 to SLAVE_COUNT);
 	signal aw_slaves_in   : axi_aw_slaves_in_t(0 to SLAVE_COUNT);
+	signal ar_masters_out : axi_ar_masters_out_t(0 to MASTER_COUNT - 1);
+	signal ar_masters_in  : axi_ar_masters_in_t(0 to MASTER_COUNT - 1);
+	signal ar_slaves_out  : axi_ar_slaves_out_t(0 to SLAVE_COUNT);
+	signal ar_slaves_in   : axi_ar_slaves_in_t(0 to SLAVE_COUNT);
 
 begin
 	reset_sync : process(aclk, aresetn) is
@@ -62,4 +66,26 @@ begin
 		slaves_in(i).aw  <= aw_slaves_in(i);
 	end generate aw_slave_connect;
 
+	axi3intercon_ar_router_inst : entity work.axi3intercon_ar_router
+		port map(
+			aclk          => aclk,
+			rst           => rst,
+			masters_out   => ar_masters_out,
+			masters_in    => ar_masters_in,
+			slaves_out    => ar_slaves_out,
+			slaves_in     => ar_slaves_in,
+			address_array => address_array,
+			mask_array    => mask_array
+		);
+
+	ar_master_connect : for i in 0 to MASTER_COUNT - 1 generate
+		ar_masters_out(i) <= masters_out(i).ar;
+		masters_in(i).ar  <= ar_masters_in(i);
+	end generate ar_master_connect;
+
+	ar_slave_connect : for i in 0 to SLAVE_COUNT - 1 generate
+		ar_slaves_out(i) <= slaves_out(i).ar;
+		slaves_in(i).ar  <= ar_slaves_in(i);
+	end generate ar_slave_connect;
+
 end architecture RTL;