From 438c23290ec9a0fc475bbfd8e4d507943aa864ce Mon Sep 17 00:00:00 2001 From: Shino Amakusa Date: Sun, 21 Aug 2016 15:41:09 +0200 Subject: [PATCH] fixed entity name of aw router --- src/axi3-interconnect-aw-router.vhd | 6 ++--- src/axi3-interconnect-aw-router_pkg.vhd | 2 +- src/axi3-interconnect.vhd | 36 +++++++++++-------------- 3 files changed, 20 insertions(+), 24 deletions(-) diff --git a/src/axi3-interconnect-aw-router.vhd b/src/axi3-interconnect-aw-router.vhd index 77706e6..353ef96 100644 --- a/src/axi3-interconnect-aw-router.vhd +++ b/src/axi3-interconnect-aw-router.vhd @@ -5,7 +5,7 @@ use ieee.numeric_std.all; use work.axi3intercon_pkg.all; use work.axi_aw_router_pkg.all; -entity axi3intecon_aw_router is +entity axi3intercon_aw_router is port( aclk : in std_logic; rst : in std_logic; @@ -16,8 +16,8 @@ entity axi3intecon_aw_router is write_locks : out write_locks_t(0 to MASTER_COUNT - 1); write_releases : in write_release_t ); -end entity axi3intecon_aw_router; +end entity axi3intercon_aw_router; -architecture RTL of axi3intecon_aw_router is +architecture RTL of axi3intercon_aw_router is begin end architecture RTL; diff --git a/src/axi3-interconnect-aw-router_pkg.vhd b/src/axi3-interconnect-aw-router_pkg.vhd index aa5409f..3a5f0fc 100644 --- a/src/axi3-interconnect-aw-router_pkg.vhd +++ b/src/axi3-interconnect-aw-router_pkg.vhd @@ -15,7 +15,7 @@ package axi_aw_router_pkg is end record write_lock_t; type write_locks_t is array (natural range <>) of write_lock_t; - subtype write_release_t is std_logic_vector(0 to MASTER_COUNT -1); + subtype write_release_t is std_logic_vector(0 to MASTER_COUNT - 1); end package axi_aw_router_pkg; diff --git a/src/axi3-interconnect.vhd b/src/axi3-interconnect.vhd index 26d9922..d88a817 100644 --- a/src/axi3-interconnect.vhd +++ b/src/axi3-interconnect.vhd @@ -17,13 +17,13 @@ entity axi3intercon is end entity axi3intercon; architecture RTL of axi3intercon is - signal rst : std_logic; - signal write_locks : write_locks_t(0 to MASTER_COUNT - 1); + signal rst : std_logic; + signal write_locks : write_locks_t(0 to MASTER_COUNT - 1); signal write_releases : write_release_t; signal aw_masters_out : axi_aw_masters_out_t(0 to MASTER_COUNT - 1); - signal aw_masters_in : axi_aw_masters_in_t(0 to MASTER_COUNT - 1); - signal aw_slaves_out : axi_aw_slaves_out_t(0 to SLAVE_COUNT - 1); - signal aw_slaves_in : axi_aw_slaves_in_t(0 to SLAVE_COUNT - 1); + signal aw_masters_in : axi_aw_masters_in_t(0 to MASTER_COUNT - 1); + signal aw_slaves_out : axi_aw_slaves_out_t(0 to SLAVE_COUNT - 1); + signal aw_slaves_in : axi_aw_slaves_in_t(0 to SLAVE_COUNT - 1); begin reset_sync : process(aclk, aresetn) is begin @@ -33,9 +33,8 @@ begin rst <= '0'; end if; end process reset_sync; - - - axi3intecon_aw_router_inst : entity work.axi3intecon_aw_router + + axi3intercon_aw_router_inst : entity work.axi3intercon_aw_router port map( aclk => aclk, rst => rst, @@ -46,18 +45,15 @@ begin write_locks => write_locks, write_releases => write_releases ); - - aw_master_connect : for i in 0 to MASTER_COUNT-1 generate - aw_masters_out(i) <= masters_out(i).aw; - masters_in(i).aw <= aw_masters_in(i); - end generate aw_master_connect; - - aw_slave_connect : for i in 0 to SLAVE_COUNT-1 generate - aw_slaves_out(i) <= slaves_out(i).aw; - slaves_in(i).aw <= aw_slaves_in(i); - end generate aw_slave_connect; - - + aw_master_connect : for i in 0 to MASTER_COUNT - 1 generate + aw_masters_out(i) <= masters_out(i).aw; + masters_in(i).aw <= aw_masters_in(i); + end generate aw_master_connect; + + aw_slave_connect : for i in 0 to SLAVE_COUNT - 1 generate + aw_slaves_out(i) <= slaves_out(i).aw; + slaves_in(i).aw <= aw_slaves_in(i); + end generate aw_slave_connect; end architecture RTL;