From 6aaf75421adf7595a9bceb35ec8ba0c52ff297d4 Mon Sep 17 00:00:00 2001 From: Shino Amakusa Date: Sun, 21 Aug 2016 14:30:27 +0200 Subject: [PATCH] finished types. wrote top-entity --- src/axi3-interconnect.vhd | 22 ++++-- src/axi3-interconnect_pkg.vhd | 129 +++++++++++++++++++++++++++++++--- 2 files changed, 136 insertions(+), 15 deletions(-) diff --git a/src/axi3-interconnect.vhd b/src/axi3-interconnect.vhd index cd15d27..bfb486a 100644 --- a/src/axi3-interconnect.vhd +++ b/src/axi3-interconnect.vhd @@ -1,19 +1,29 @@ library ieee; + use ieee.std_logic_1164.all; use ieee.numeric_std.all; +-- "work" denotes the curent library. Similar to this in C++, C# etc... +use work.axi3intercon_pkg.all; entity axi3intercon is - port ( - aclk : in std_logic; - aresetn : in std_logic + generic( + constant MASTER_COUNT : natural := 1; + constant SLAVE_COUNT : natural := 1 + ); + port( + aclk : in std_logic; + aresetn : in std_logic; + masters_in : out axi_masters_in(0 to MASTER_COUNT - 1); + masters_out : in axi_masters_out(0 to MASTER_COUNT - 1); + slaves_in : out axi_masters_in(0 to SLAVE_COUNT - 1); + slaves_out : in axi_masters_out(0 to SLAVE_COUNT - 1) ); end entity axi3intercon; architecture RTL of axi3intercon is signal rst : std_logic; begin - - reset_sync : process(aclk, aresetn) is + reset_sync : process(aclk, aresetn) is begin if aresetn = '0' then rst <= '1'; @@ -21,7 +31,5 @@ begin rst <= '0'; end if; end process reset_sync; - - end architecture RTL; diff --git a/src/axi3-interconnect_pkg.vhd b/src/axi3-interconnect_pkg.vhd index f3b1982..8d5e845 100644 --- a/src/axi3-interconnect_pkg.vhd +++ b/src/axi3-interconnect_pkg.vhd @@ -3,17 +3,42 @@ use ieee.std_logic_1164.all; use ieee.numeric_std.all; package axi3intercon_pkg is - constant RID_MASTER_BITS : natural := 8; - constant RID_SLAVE_BITS : natural := 10; - constant WID_MASTER_BITS : natural := 8; - constant WID_SLAVE_BITS : natural := 10; + -- Slave bits have to be more. SLAVE_BITS = MASTER_BITS + log_2(MASTER_COUNT) + -- Master ID is padded onto ID to identify the transfer internally in the crossbar + -- This is defined in AXI-3 and -4 Standard. + constant RID_MASTER_BITS : natural := 12; + constant RID_SLAVE_BITS : natural := 14; + constant WID_MASTER_BITS : natural := 12; + constant WID_SLAVE_BITS : natural := 14; constant DATA_BITS : natural := 32; constant DATA_STROBES : natural := (DATA_BITS / 8); constant ADDRESS_BITS : natural := 32; - constant MASTER_COUNT : natural := 2; - constant SLAVE_COUNT : natural := 2; + constant USER_BITS : natural := 4; + + -- Constant definitions for signals + + --Definitions for burst size + constant AXI_SIZE_1 : std_logic_vector(2 downto 0) := (others => '0'); + constant AXI_SIZE_2 : std_logic_vector(2 downto 0) := "001"; + constant AXI_SIZE_4 : std_logic_vector(2 downto 0) := "010"; + constant AXI_SIZE_8 : std_logic_vector(2 downto 0) := "011"; + constant AXI_SIZE_16 : std_logic_vector(2 downto 0) := "100"; + constant AXI_SIZE_32 : std_logic_vector(2 downto 0) := "101"; + constant AXI_SIZE_64 : std_logic_vector(2 downto 0) := "110"; + constant AXI_SIZE_128 : std_logic_vector(2 downto 0) := "111"; + + -- Definitions for response vector + constant AXI_RESP_OKAY : std_logic_vector(1 downto 0) := "00"; + constant AXI_RESP_EXOKAY : std_logic_vector(1 downto 0) := "01"; + constant AXI_RESP_SLVERR : std_logic_vector(1 downto 0) := "10"; + constant AXI_RESP_DECERR : std_logic_vector(1 downto 0) := "11"; + + -- Definitions for lock locked transactions (only AXI 3 supports locked access mode) + constant AXI_LOCK_NORMAL : std_logic_vector(1 downto 0) := "00"; + constant AXI_RESP_EXCLUSIVE : std_logic_vector(1 downto 0) := "01"; + constant AXI_RESP_LOCKED : std_logic_vector(1 downto 0) := "10"; -- type declarations for AW channel type master_aw_out is record @@ -83,7 +108,7 @@ package axi3intercon_pkg is wdata : std_logic_vector(DATA_BITS - 1 downto 0); wstrb : std_logic_vector(DATA_STROBES - 1 downto 0); wlast : std_logic; - wuser : std_logic; -- user defined + wuser : std_logic_vector(USER_BITS - 1 downto 0); -- user defined wvalid : std_logic; end record master_w_out; @@ -92,7 +117,7 @@ package axi3intercon_pkg is wdata : std_logic_vector(DATA_BITS - 1 downto 0); wstrb : std_logic_vector(DATA_STROBES - 1 downto 0); wlast : std_logic; - wuser : std_logic; -- user defined + wuser : std_logic_vector(USER_BITS - 1 downto 0); -- user defined wvalid : std_logic; end record slave_w_in; @@ -101,6 +126,94 @@ package axi3intercon_pkg is end record master_w_in; subtype slave_w_out is master_w_in; + + -- Type declarations for R channel + type master_r_in is record + rid : std_logic_vector(RID_MASTER_BITS - 1 downto 0); + rdata : std_logic_vector(DATA_BITS - 1 downto 0); + rresp : std_logic_vector(1 downto 0); + rlast : std_logic; + ruser : std_logic_vector(USER_BITS - 1 downto 0); + rvalid : std_logic; + end record master_r_in; + + type slave_r_out is record + rid : std_logic_vector(RID_SLAVE_BITS - 1 downto 0); + rdata : std_logic_vector(DATA_BITS - 1 downto 0); + rresp : std_logic_vector(1 downto 0); + rlast : std_logic; + ruser : std_logic_vector(USER_BITS - 1 downto 0); + rvalid : std_logic; + end record slave_r_out; + + type master_r_out is record + rready : std_logic; + end record master_r_out; + + subtype slave_r_in is master_r_out; + + -- Type declarations for B channel + type master_b_in is record + bid : std_logic_vector(WID_MASTER_BITS - 1 downto 0); + bresp : std_logic_vector(1 downto 0); + buser : std_logic_vector(USER_BITS - 1 downto 0); + bvalid : std_logic; + end record master_b_in; + + type slave_b_out is record + bid : std_logic_vector(WID_SLAVE_BITS - 1 downto 0); + bresp : std_logic_vector(1 downto 0); + buser : std_logic_vector(USER_BITS - 1 downto 0); + bvalid : std_logic; + end record slave_b_out; + + type master_b_out is record + bready : std_logic; + end record master_b_out; + + subtype slave_b_in is master_b_out; + + -- Combined definitions + + type axi_master_in is record + aw : master_aw_in; + ar : master_ar_in; + w : master_w_in; + r : master_r_in; + b : master_b_in; + end record axi_master_in; + + type axi_master_out is record + aw : master_aw_out; + ar : master_ar_out; + w : master_w_out; + r : master_r_out; + b : master_b_out; + end record axi_master_out; + + type axi_slave_in is record + aw : slave_aw_in; + ar : slave_ar_in; + w : slave_w_in; + r : slave_r_in; + b : slave_b_in; + end record axi_slave_in; + + type axi_slave_out is record + aw : slave_aw_out; + ar : slave_ar_out; + w : slave_w_out; + r : slave_r_out; + b : slave_b_out; + end record axi_slave_out; + + -- Array definitions + + type axi_masters_in is array (natural range <>) of axi_master_in; + type axi_masters_out is array (natural range <>) of axi_master_out; + type axi_slaves_in is array (natural range <>) of axi_slave_in; + type axi_slaves_out is array (natural range <>) of axi_slave_out; + end package axi3intercon_pkg; -- package body axi3intercon_pkg is