diff --git a/.library_mapping.xml b/.library_mapping.xml
index d562e70..0247597 100644
--- a/.library_mapping.xml
+++ b/.library_mapping.xml
@@ -1,6 +1,6 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <com.sigasi.hdt.shared.librarymapping.model:LibraryMappings xmlns:com.sigasi.hdt.shared.librarymapping.model="com.sigasi.hdt.vhdl.scoping.librarymapping" Version="2">
-  <Mappings Location="src" Library="axi3intercon"/>
+  <Mappings Location="src" Library="axi3interconnect"/>
   <Mappings Location="Common Libraries/IEEE" Library="ieee"/>
   <Mappings Location="Common Libraries" Library="not mapped"/>
   <Mappings Location="Common Libraries/STD" Library="std"/>
diff --git a/src/axi3-interconnect_pkg.vhd b/src/axi3-interconnect_pkg.vhd
index 0a3fdf6..f3b1982 100644
--- a/src/axi3-interconnect_pkg.vhd
+++ b/src/axi3-interconnect_pkg.vhd
@@ -44,7 +44,7 @@ package axi3intercon_pkg is
 		awvalid : std_logic;            -- Data valid
 	end record slave_aw_in;
 
-	alias slave_aw_out is master_aw_in;
+	subtype slave_aw_out is master_aw_in;
 
 	-- type decalatations for AR cahnnel
 	type master_ar_out is record
@@ -75,7 +75,7 @@ package axi3intercon_pkg is
 		arvalid : std_logic;            -- Data valid
 	end record slave_ar_in;
 
-	alias slave_ar_out is master_ar_in;
+	subtype slave_ar_out is master_ar_in;
 
 	-- type decalarations for W channel
 	type master_w_out is record
@@ -100,8 +100,8 @@ package axi3intercon_pkg is
 		wready : std_logic;
 	end record master_w_in;
 
-	alias slave_w_out is master_w_in;
+	subtype slave_w_out is master_w_in;
 end package axi3intercon_pkg;
 
-package body axi3intercon_pkg is
-end package body axi3intercon_pkg;
+-- package body axi3intercon_pkg is
+-- end package body axi3intercon_pkg;