commit c35444e55a6d3112edae5613c7cedda7e2c8fe78 Author: Shino Amakusa Date: Sat Aug 20 14:43:06 2016 +0200 started type definitions diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..b25c15b --- /dev/null +++ b/.gitignore @@ -0,0 +1 @@ +*~ diff --git a/.library_mapping.xml b/.library_mapping.xml new file mode 100644 index 0000000..d562e70 --- /dev/null +++ b/.library_mapping.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/.project b/.project new file mode 100644 index 0000000..937934c --- /dev/null +++ b/.project @@ -0,0 +1,45 @@ + + + axi3-interconnect + + + + + + org.eclipse.xtext.ui.shared.xtextBuilder + + + + + + com.sigasi.hdt.vhdl.ui.vhdlNature + org.eclipse.xtext.ui.shared.xtextNature + + + + Common Libraries + 2 + virtual:/virtual + + + Common Libraries/DRAG_REUSABLE_LIBRARIES_HERE.txt + 1 + sigasiresource:/vhdl/readme2.txt + + + Common Libraries/IEEE + 2 + sigasiresource:/vhdl/2008/IEEE + + + Common Libraries/STD + 2 + sigasiresource:/vhdl/2008/STD + + + Common Libraries/IEEE/Synopsys + 2 + sigasiresource:/vhdl/2008/IEEE%20Synopsys + + + diff --git a/.settings/org.eclipse.core.resources.prefs b/.settings/org.eclipse.core.resources.prefs new file mode 100644 index 0000000..240a6e2 --- /dev/null +++ b/.settings/org.eclipse.core.resources.prefs @@ -0,0 +1,5 @@ +eclipse.preferences.version=1 +encoding//Common\ Libraries/IEEE=utf-8 +encoding//Common\ Libraries/IEEE/Synopsys=utf-8 +encoding//Common\ Libraries/STD=utf-8 +encoding/Common\ Libraries=utf-8 diff --git a/src/axi3-interconnect.vhd b/src/axi3-interconnect.vhd new file mode 100644 index 0000000..cd15d27 --- /dev/null +++ b/src/axi3-interconnect.vhd @@ -0,0 +1,27 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity axi3intercon is + port ( + aclk : in std_logic; + aresetn : in std_logic + ); +end entity axi3intercon; + +architecture RTL of axi3intercon is + signal rst : std_logic; +begin + + reset_sync : process(aclk, aresetn) is + begin + if aresetn = '0' then + rst <= '1'; + elsif rising_edge(aclk) then + rst <= '0'; + end if; + end process reset_sync; + + + +end architecture RTL; diff --git a/src/axi3-interconnect_pkg.vhd b/src/axi3-interconnect_pkg.vhd new file mode 100644 index 0000000..0a3fdf6 --- /dev/null +++ b/src/axi3-interconnect_pkg.vhd @@ -0,0 +1,107 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +package axi3intercon_pkg is + constant RID_MASTER_BITS : natural := 8; + constant RID_SLAVE_BITS : natural := 10; + constant WID_MASTER_BITS : natural := 8; + constant WID_SLAVE_BITS : natural := 10; + + constant DATA_BITS : natural := 32; + constant DATA_STROBES : natural := (DATA_BITS / 8); + constant ADDRESS_BITS : natural := 32; + + constant MASTER_COUNT : natural := 2; + constant SLAVE_COUNT : natural := 2; + + -- type declarations for AW channel + type master_aw_out is record + awid : std_logic_vector(WID_MASTER_BITS - 1 downto 0); -- Write transaction ID + awaddr : std_logic_vector(DATA_BITS - 1 downto 0); -- Write address + awlen : std_logic_vector(7 downto 0); -- Burst length - 1; + awsize : std_logic_vector(2 downto 0); -- Maximum size of the beat + awburst : std_logic_vector(1 downto 0); -- Burst type + awlock : std_logic_vector(1 downto 0); -- Lock info + awcache : std_logic_vector(3 downto 0); -- caching info + awprot : std_logic_vector(2 downto 0); -- protection info + awvalid : std_logic; -- Data valid + end record master_aw_out; + + type master_aw_in is record + awready : std_logic; + end record master_aw_in; + + type slave_aw_in is record + awid : std_logic_vector(WID_SLAVE_BITS - 1 downto 0); -- Write transaction ID + awaddr : std_logic_vector(DATA_BITS - 1 downto 0); -- Write address + awlen : std_logic_vector(7 downto 0); -- Burst length - 1; + awsize : std_logic_vector(2 downto 0); -- Maximum size of the beat + awburst : std_logic_vector(1 downto 0); -- Burst type + awlock : std_logic_vector(1 downto 0); -- Lock info + awcache : std_logic_vector(3 downto 0); -- caching info + awprot : std_logic_vector(2 downto 0); -- protection info + awvalid : std_logic; -- Data valid + end record slave_aw_in; + + alias slave_aw_out is master_aw_in; + + -- type decalatations for AR cahnnel + type master_ar_out is record + arid : std_logic_vector(WID_MASTER_BITS - 1 downto 0); -- Write transaction ID + araddr : std_logic_vector(DATA_BITS - 1 downto 0); -- Write start address + arlen : std_logic_vector(7 downto 0); -- Burst length - 1; + arsize : std_logic_vector(2 downto 0); -- Maximum size of the beat + arburst : std_logic_vector(1 downto 0); -- Burst type + arlock : std_logic_vector(1 downto 0); -- Lock info + arcache : std_logic_vector(3 downto 0); -- caching info + arprot : std_logic_vector(2 downto 0); -- protection info + arvalid : std_logic; -- Data valid + end record master_ar_out; + + type master_ar_in is record + awready : std_logic; + end record master_ar_in; + + type slave_ar_in is record + arid : std_logic_vector(WID_SLAVE_BITS - 1 downto 0); -- Read transaction ID + araddr : std_logic_vector(DATA_BITS - 1 downto 0); -- Read start address + arlen : std_logic_vector(7 downto 0); -- Burst length - 1; + arsize : std_logic_vector(2 downto 0); -- Maximum size of the beat + arburst : std_logic_vector(1 downto 0); -- Burst type + arlock : std_logic_vector(1 downto 0); -- Lock info + arcache : std_logic_vector(3 downto 0); -- caching info + arprot : std_logic_vector(2 downto 0); -- protection info + arvalid : std_logic; -- Data valid + end record slave_ar_in; + + alias slave_ar_out is master_ar_in; + + -- type decalarations for W channel + type master_w_out is record + wid : std_logic_vector(WID_MASTER_BITS - 1 downto 0); + wdata : std_logic_vector(DATA_BITS - 1 downto 0); + wstrb : std_logic_vector(DATA_STROBES - 1 downto 0); + wlast : std_logic; + wuser : std_logic; -- user defined + wvalid : std_logic; + end record master_w_out; + + type slave_w_in is record + wid : std_logic_vector(WID_SLAVE_BITS - 1 downto 0); + wdata : std_logic_vector(DATA_BITS - 1 downto 0); + wstrb : std_logic_vector(DATA_STROBES - 1 downto 0); + wlast : std_logic; + wuser : std_logic; -- user defined + wvalid : std_logic; + end record slave_w_in; + + type master_w_in is record + wready : std_logic; + end record master_w_in; + + alias slave_w_out is master_w_in; +end package axi3intercon_pkg; + +package body axi3intercon_pkg is +end package body axi3intercon_pkg;