From c660af5df09044281deb6b71bbd9288d666ec7b6 Mon Sep 17 00:00:00 2001 From: Shino Amakusa Date: Sun, 21 Aug 2016 20:54:02 +0200 Subject: [PATCH] fixed aw router to fut VHDL93 --- src/axi3-interconnect-aw-router.vhd | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/src/axi3-interconnect-aw-router.vhd b/src/axi3-interconnect-aw-router.vhd index e42515d..3392046 100644 --- a/src/axi3-interconnect-aw-router.vhd +++ b/src/axi3-interconnect-aw-router.vhd @@ -26,9 +26,14 @@ architecture RTL of axi3intercon_aw_router is type aw_states_t is array (0 to MASTER_COUNT - 1) of aw_state_t; signal aw_states : aw_states_t; signal write_locks_s : write_locks_t(0 to MASTER_COUNT - 1); + signal awready_s : std_logic_vector(0 to MASTER_COUNT - 1); begin write_locks <= write_locks_s; + awready_gen : for i in 0 to MASTER_COUNT - 1 generate + masters_in(i).awready <= awready_s(i); + end generate awready_gen; + aw_router : process(clk, rst) is variable slave_idx : integer range 0 to SLAVE_COUNT := SLAVE_COUNT; -- 1 more slave than connected for handling bad requests. variable slave_in_use : std_logic_vector(0 to SLAVE_COUNT); @@ -46,22 +51,22 @@ begin begin if rst = '1' then for i in 0 to MASTER_COUNT - 1 loop - aw_states(i) <= AW_READY; - masters_in(i).awready <= '1'; - slave_in_use := (others => '0'); + aw_states(i) <= AW_READY; end loop; + awready_s <= (others => '1'); + slave_in_use := (others => '0'); elsif rising_edge(clk) then for i in 0 to MASTER_COUNT - 1 loop -- Loop for every master case aw_states(i) is when AW_READY => masters_in(i).awready <= '1'; - if masters_out(i).awvalid = '1' and masters_in(i).awready = '1' then -- check awready. just to prevent glitches + if masters_out(i).awvalid = '1' and awready_s(i) = '1' then -- check awready. just to prevent glitches slave_idx := calculate_slave(masters_out(i).awaddr, address_array, mask_array); if slave_in_use(slave_idx) /= '1' then write_locks_s(i).slave_idx <= slave_idx; write_locks_s(i).locked <= '1'; slave_in_use(slave_idx) := '1'; - masters_in(i).awready <= '0'; + awready_s(i) <= '0'; -- output request to slave slaves_in(slave_idx).awaddr <= masters_out(i).awaddr; slaves_in(slave_idx).awid <= std_logic_vector(to_unsigned(i, WID_SLAVE_BITS - WID_MASTER_BITS - 1)) & masters_out(i).awid;