library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library design;
use design.all;
use design.axi3intercon_pkg.all;


entity bench is

end entity bench;

architecture sim of bench is

	constant addresses : axi_slave_addresses_t := (0 => (others => '1'));
	constant masks	   : axi_slave_addresses_t := (0 => (0 => '0', 1 => '0', others => '1'));

	signal slaves_out  : axi_slaves_out_t(0 to 0);
	signal masters_out : axi_masters_out_t(0 to 0);
	signal masters_in  : axi_masters_in_t(0 to 0);

	signal aclk    : std_logic;
	signal aresetn : std_logic;


begin  -- architecture sim


	clkgen : process is
	begin
		aclk <= '0';
		wait for 20 ns;
		aclk <= '1';
		wait for 20 ns;
	end process clkgen;

	rstgen : process is
	begin
		aresetn <= '0';
		wait for 30 ns;
		aresetn <= '1';
		wait;
	end process rstgen;

	test : process is
	begin
		wait until rising_edge(aclk);
		wait until rising_edge(aclk);
		wait for 100 ns;

		masters_out(0).w.wvalid <= '0';
		masters_out(0).w.wlast	<= '0';

		wait until rising_edge(aclk);

		masters_out(0).ar.arid	 <= (3 => '0', others => '1');
		masters_out(0).ar.araddr <= (2 => '1', 4 => '1', others => '0');

		masters_out(0).ar.arlen	  <= std_logic_vector(to_unsigned(9, 8));
		masters_out(0).ar.arburst <= (others => '0');
		masters_out(0).ar.arprot  <= (others => '0');
		masters_out(0).ar.arsize  <= (1	     => '1', others => '0');
		masters_out(0).ar.arvalid <= '1';
		wait until rising_edge(aclk) and masters_in(0).ar.arready = '1';
		masters_out(0).ar.arvalid <= '0';


		wait until rising_edge(aclk);
		-- Issue write request
		masters_out(0).aw.awid	  <= (5	     => '1', others => '0');
		masters_out(0).aw.awaddr  <= (4	     => '1', others => '0');
		masters_out(0).aw.awlen	  <= std_logic_vector(to_unsigned(1, 8));
		masters_out(0).aw.awsize  <= (others => '0');
		masters_out(0).aw.awburst <= (others => '0');
		masters_out(0).aw.awlock  <= (others => '0');
		masters_out(0).aw.awcache <= (others => '0');
		masters_out(0).aw.awprot  <= (others => '0');
		masters_out(0).aw.awvalid <= '1';
		wait until rising_edge(aclk) and masters_in(0).aw.awready = '1';
		masters_out(0).aw.awvalid <= '0';

		masters_out(0).w.wstrb	<= (others => '1');
		masters_out(0).w.wdata	<= x"DEADBEEF";
		masters_out(0).w.wlast	<= '0';
		masters_out(0).w.wid	<= (5	   => '1', others => '0');
		masters_out(0).w.wvalid <= '1';
		wait until rising_edge(aclk) and masters_in(0).w.wready = '1';
		masters_out(0).w.wvalid <= '1';
		masters_out(0).w.wdata	<= x"CAFEBABE";
		masters_out(0).w.wlast	<= '1';
		wait until rising_edge(aclk) and masters_in(0).w.wready = '1';
		masters_out(0).w.wvalid <= '0';


		wait;
	end process;

	b_acceptor : process is
	begin
		masters_out(0).b.bready <= '0';
		wait until rising_edge(aclk) and masters_in(0).b.bvalid = '1';
		report "b_acceptor: Received B channel response wit BID " &
			integer'image(to_integer(unsigned(masters_in(0).b.bid)));
		masters_out(0).b.bready <= '1';
		wait until rising_edge(aclk);

	end process b_acceptor;

	read_acceptor : process is
	begin
		masters_out(0).r.rready <= '0';
		wait until rising_edge(aclk) and masters_in(0).r.rvalid = '1';
		report "read_acceptor: Received read with RID " &
			integer'image(to_integer(unsigned(masters_in(0).r.rid)));
		report "read_acceptor: RLAST is " & std_logic'image(masters_in(0).r.rlast);
		masters_out(0).r.rready <= '1';
		wait until rising_edge(aclk);

	end process read_acceptor;

	axi3intercon_1 : entity design.axi3intercon
		port map (
			aclk	      => aclk,
			aresetn	      => aresetn,
			masters_in    => masters_in,
			masters_out   => masters_out,
			slaves_in     => open,
			slaves_out    => slaves_out,
			address_array => addresses,
			mask_array    => masks);

end architecture sim;