library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity axi3intercon is
	port (
		aclk : in std_logic;
		aresetn : in std_logic
	);
end entity axi3intercon;

architecture RTL of axi3intercon is
	signal rst : std_logic;
begin
	
	reset_sync : process(aclk, aresetn)  is
	begin
		if aresetn = '0' then
			rst <= '1';
		elsif rising_edge(aclk) then
			rst <= '0';
		end if;
	end process reset_sync;
	
	

end architecture RTL;