library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.axi3intercon_pkg.all;
use work.axi_ar_router_pkg.all;

entity axi3intercon_ar_router is
	port(
		aclk          : in  std_logic;
		rst           : in  std_logic;
		masters_out   : in  axi_ar_masters_out_t(0 to MASTER_COUNT - 1);
		masters_in    : out axi_ar_masters_in_t(0 to MASTER_COUNT - 1);
		slaves_out    : in  axi_ar_slaves_out_t(0 to SLAVE_COUNT);
		slaves_in     : out axi_ar_slaves_in_t(0 to SLAVE_COUNT);
		address_array : in  axi_slave_addresses_t(0 to SLAVE_COUNT - 1);
		mask_array    : in  axi_slave_addresses_t(0 to SLAVE_COUNT - 1)
	);
end entity axi3intercon_ar_router;

architecture RTL of axi3intercon_ar_router is
	alias clk is aclk;
	type ar_state_t is (AR_READY, AR_ACTIVE);
	type ar_states_t is array (0 to MASTER_COUNT - 1) of ar_state_t;
	signal ar_states : ar_states_t;
	signal arready_s : std_logic_vector(0 to MASTER_COUNT - 1);
	type slave_indexes_t is array (0 to MASTER_COUNT - 1) of integer range 0 to SLAVE_COUNT;
begin
	arready_gen : for i in 0 to MASTER_COUNT - 1 generate
		masters_in(i).arready <= arready_s(i);
	end generate arready_gen;

	ar_router : process(clk, rst) is
		variable slave_idx    : slave_indexes_t;
		variable slave_in_use : std_logic_vector(0 to SLAVE_COUNT);

	begin
		if rst = '1' then
			for i in 0 to MASTER_COUNT - 1 loop
				ar_states(i) <= AR_READY;
			end loop;
			for i in 0 to SLAVE_COUNT loop
				slaves_in(i).arvalid <= '0';
			end loop;
			slave_in_use := (others => '0');
			arready_s    <= (others => '1');
		elsif rising_edge(clk) then
			for i in 0 to MASTER_COUNT - 1 loop -- Loop for every master
				case ar_states(i) is
					when AR_READY =>
						arready_s(i) <= '1';
						if masters_out(i).arvalid = '1' and arready_s(i) = '1' then
							slave_idx(i) := calculate_slave(masters_out(i).araddr, address_array, mask_array);
							if slave_in_use(slave_idx(i)) /= '1' then
								slave_in_use(slave_idx(i))      := '1';
								masters_in(i).arready           <= '0';
								-- Write request to slave
								slaves_in(slave_idx(i)).araddr  <= masters_out(i).araddr;
								slaves_in(slave_idx(i)).arid    <= std_logic_vector(to_unsigned(i, WID_SLAVE_BITS - WID_MASTER_BITS)) & masters_out(i).arid;
								slaves_in(slave_idx(i)).arburst <= masters_out(i).arburst;
								slaves_in(slave_idx(i)).arcache <= masters_out(i).arcache;
								slaves_in(slave_idx(i)).arlen   <= masters_out(i).arlen;
								slaves_in(slave_idx(i)).arlock  <= masters_out(i).arlock;
								slaves_in(slave_idx(i)).arprot  <= masters_out(i).arprot;
								slaves_in(slave_idx(i)).arsize  <= masters_out(i).arsize;
								slaves_in(slave_idx(i)).arvalid <= '1';
								ar_states(i)                    <= AR_ACTIVE;
							end if;
						end if;
					when AR_ACTIVE =>
						if slaves_out(slave_idx(i)).arready = '1' then
							slaves_in(slave_idx(i)).arvalid <= '0';
							ar_states(i)                    <= AR_READY;
							slave_in_use(slave_idx(i))      := '0';
						end if;
				end case;

			end loop;
		end if;
	end process ar_router;

end architecture RTL;