207 lines
6.6 KiB
VHDL
207 lines
6.6 KiB
VHDL
-------------------------------------------------------------------------------
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-- Title : MachXO2 Serial Configuration
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-- Project : tiny-xo2
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-------------------------------------------------------------------------------
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-- File : top.vhd
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-- Author : Mario Hüttel <mario.huettel@gmx.net>
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-- Company :
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-- Created : 2017-11-21
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-- Last update: 2017-11-23
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-- Platform :
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-- Standard : VHDL'93/02
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-------------------------------------------------------------------------------
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-- Description:
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-------------------------------------------------------------------------------
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-- Copyright (c) 2017 GPLv2
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity config_top is
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generic (
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CLKDIV : integer := 10);
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port (
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clk : in std_logic; -- input clock 12 MHz
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dts : in std_logic; -- DTS Strobe signal
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rst_out : out std_logic;
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uart_tx : out std_logic; -- UART TX
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uart_rx : in std_logic); -- UART RX
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end entity config_top;
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architecture RTL of config_top is
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type fsm_state_t is (IDLE, CMD, EXEC, REPLY, HANG);
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----------------- RESET LOGIC ------------------------------
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signal dts_sync : std_logic_vector(2 downto 0) := (others => '0');
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signal rst : std_logic; -- reset (high active)
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----------------- UART RX ----------------------------------
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signal data_rx : std_logic_vector(7 downto 0);
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signal byte_ready_rx : std_logic;
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signal error_rx : std_logic;
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----------------- UART TX ----------------------------------
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signal data_tx : std_logic_vector(7 downto 0);
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signal byte_ready_tx : std_logic;
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signal busy_tx : std_logic;
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signal config_busy : std_logic := '1'; -- indicates that the core is in configuration/waiting mode
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-- and the user logic has to stay in reset
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signal config_active : std_logic := '1'; -- configuration FSM active
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---------------------------- Wishbone Bus -------------------------------------
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signal wb_cyc : std_logic;
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signal wb_stb : std_logic;
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signal wb_we : std_logic;
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signal wb_adr : std_logic_vector(7 downto 0);
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signal wb_dat_in : std_logic_vector(7 downto 0);
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signal wb_dat_out : std_logic_vector(7 downto 0);
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signal wb_ack : std_logic;
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-------------------------------- State machine -----------------------------------
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signal state : fsm_state_t;
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signal reply_is_error : std_logic;
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signal bytecounter : integer range 0 to 3 := 0;
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begin -- architecture RTL
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-----------------------------------------------------------------------------
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------------------------------ Wishbone EFB for Config ----------------------
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-----------------------------------------------------------------------------
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efb_ufr_1 : entity work.efb_ufr
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port map (
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wb_clk_i => clk,
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wb_rst_i => rst,
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wb_cyc_i => wb_cyc,
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wb_stb_i => wb_stb,
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wb_we_i => wb_we,
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wb_adr_i => wb_adr,
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wb_dat_i => wb_dat_in,
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wb_dat_o => wb_dat_out,
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wb_ack_o => wb_ack,
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wbc_ufm_irq => open);
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uart_rx_1 : entity work.uart_rx
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port map (
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clk => clk,
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rst => rst,
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data => data_rx,
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byte_ready => byte_ready_rx,
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error => error_rx,
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ckDiv => CLKDIV,
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parityEnable => '1',
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parityOdd => '0',
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twoStopBits => '0',
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rx => uart_rx);
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uart_tx_1 : entity work.uart_tx
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port map (
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clk => clk,
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rst => rst,
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data => data_tx,
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byte_ready => byte_ready_tx,
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busy => busy_tx,
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ckDiv => CLKDIV,
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parityEnable => '1',
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parityOdd => '0',
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twoStopBits => '0',
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tx => uart_tx);
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-- set config_busy on reset and wait 0.25s. If FSM is not active
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-- deassert config_busy
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timeout_counter_busy_gen : process(clk, rst) is
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variable cnt : integer range 0 to 3000000 := 3000000; -- 0.25 sec counter
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begin
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if rst = '1' then
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cnt := 3000000;
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config_busy <= '1';
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elsif rising_edge(clk) then
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config_busy <= '1';
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if cnt /= 0 then
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cnt := cnt - 1
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else
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if config_active = '0' then
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config_busy <= '0';
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end if;
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end if;
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end if;
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end process timeout_counter_busy_gen;
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-- Generate reset pulse on rising edge of dts input
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reset_gen : process(clk) is
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begin
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if rising_edge(clk) then
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rst <= '0';
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dts_sync <= dts_sync(1 downto 0) & dts; -- Shif register (sync and edge detect)
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if (dts_sync(2 downto 1) = "01") then -- rising edge of DTS
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rst <= '1';
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end if;
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end if;
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end process reset_gen;
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-- hold user logic in reset until config finished or timeout
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user_logic_reset_gen : process(clk, rst) is
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begin
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if rst = '1' then
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rst_out <= '1';
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elsif rising_edge(clk) then
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if config_busy = '0' then
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rst_out <= '0';
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end if;
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end if;
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end process user_logic_reset_gen;
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controlFSM : process (clk, rst) is
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begin -- process controlFSM
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if rst = '1' then
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state <= IDLE;
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config_active <= '0';
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bytecounter <= 0;
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reply_is_error <= '0';
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-- Wishbone
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wb_cyc <= '0';
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wb_stb <= '0';
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wb_adr <= (others => '0');
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wb_dat_in <= (others => '0');
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-- UART TX
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data_tx <= (others => '0');
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byte_ready_tx <= '0';
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elsif rising_edge(clk) then
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case state is
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when IDLE =>
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if byte_ready_rx = '1' and data_rx = x"D5" then -- Serial byte received. Is it the preambel?
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state <= CMD;
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bytecounter <= 0;
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end if;
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when CMD =>
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if byte_ready_rx = '1' then
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-- TODO: Byte received. Do something
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end if;
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when EXEC =>
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null; -- TODO: handle Wishbone communication
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when REPLY =>
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-- TODO: if reply_is_error = '1' then: wait for response that
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-- indicates that the error is handled. Then switch back to command
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-- mode. Else; Just wait for response to be sent.
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null;
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when HANG =>
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state <= HANG; -- End of FSM. Only way out is a reset
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end case;
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end if;
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end process controlFSM;
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------ Asynchronous output assignments ---------------
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end architecture RTL;
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