121 lines
3.5 KiB
VHDL
121 lines
3.5 KiB
VHDL
-------------------------------------------------------------------------------
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-- Title : MachXO2 Serial Configuration
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-- Project : tiny-xo2
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-------------------------------------------------------------------------------
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-- File : top.vhd
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-- Author : マリオ <mario.huettel@gmx.net>
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-- Company :
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-- Created : 2017-11-21
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-- Last update: 2017-11-21
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-- Platform :
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-- Standard : VHDL'93/02
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-------------------------------------------------------------------------------
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-- Description:
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-------------------------------------------------------------------------------
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-- Copyright (c) 2017 GPLv2
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity config_top is
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generic (
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CLKDIV : integer := 10);
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port (
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clk : in std_logic; -- input clock 12 MHz
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dts : in std_logic; -- DTS Strobe signal
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rst_out : out std_logic;
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uart_tx : out std_logic; -- UART TX
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uart_rx : in std_logic); -- UART RX
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end entity config_top;
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architecture RTL of config_top is
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----------------- RESET LOGIC ------------------------------
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signal dts_sync : std_logic_vector(2 downto 0) := (others => '0');
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signal rst : std_logic; -- reset (high active)
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----------------- UART RX ----------------------------------
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signal data_rx : std_logic_vector(7 downto 0);
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signal byte_ready_rx : std_logic;
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signal error_rx : std_logic;
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----------------- UART TX ----------------------------------
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signal data_tx : std_logic_vector(7 downto 0);
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signal byte_ready_tx : std_logic;
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signal busy_tx : std_logic;
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signal config_busy : std_logic := '1'; -- indicates that the core is in configuration/waiting mode
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-- and the user logic has to stay in reset
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begin -- architecture RTL
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uart_rx_1 : entity work.uart_rx
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port map (
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clk => clk,
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rst => rst,
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data => data_rx,
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byte_ready => byte_ready_rx,
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error => error_rx,
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ckDiv => CLKDIV,
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parityEnable => '1',
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parityOdd => '0',
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twoStopBits => '0',
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rx => uart_rx);
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uart_tx_1 : entity work.uart_tx
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port map (
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clk => clk,
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rst => rst,
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data => data_tx,
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byte_ready => byte_ready_tx,
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busy => busy_tx,
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ckDiv => CLKDIV,
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parityEnable => '1',
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parityOdd => '0',
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twoStopBits => '0',
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tx => uart_tx);
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timeout_counter_gen : process(clk) is
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variable cnt : integer range 0 to 40000;
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begin
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-- TODO: implement timeout counter
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end process timeout_counter_gen;
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-- Generate reset pulse on rising edge of dts input
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reset_gen : process(clk) is
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begin
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if rising_edge(clk) then
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rst <= '0';
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dts_sync <= dts_sync(1 downto 0) & dts; -- Shif register (sync and edge detect)
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if (dts_sync(2 downto 1) = "01") then -- rising edge of DTS
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rst <= '1';
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end if;
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end if;
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end process reset_gen;
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-- hold user logic in reset until config finished or timeout
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user_logic_reset_gen : process(clk, rst) is
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begin
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if rst = '1' then
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rst_out <= '1';
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elsif rising_edge(clk) then
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if config_busy = '0' then
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rst_out <= '0';
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end if;
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end if;
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end process user_logic_reset_gen;
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------ Asynchronous output assignments ---------------
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end architecture RTL;
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