119 lines
2.0 KiB
VHDL
119 lines
2.0 KiB
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity test is
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end entity test;
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architecture bench of test is
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signal clk : std_logic;
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signal rst : std_logic := '1';
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signal dv : std_logic;
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signal rx : std_logic_vector(1 downto 0);
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signal mdc : std_logic;
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signal mdio : std_logic;
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signal led : std_logic_vector(1 downto 0);
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signal ws : std_logic;
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begin -- architecture bench
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top_1 : entity work.top
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port map (
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clk => clk,
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rst => rst,
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mdio => mdio,
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mdc => mdc,
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rx => rx,
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dv => dv,
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led1 => led(0),
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led2 => led(1),
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ws_out => ws);
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clkgen : process is
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begin
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clk <= '0';
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wait for 10 ns;
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clk <= '1';
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wait for 10 ns;
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end process clkgen;
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sendphy : process is
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procedure sendRMII(byte : in std_logic_vector(7 downto 0)) is
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begin
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wait until falling_edge(clk);
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dv <= '1';
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rx <= byte(1 downto 0);
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wait until falling_edge(clk);
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rx <= byte(3 downto 2);
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wait until falling_edge(clk);
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rx <= byte(5 downto 4);
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wait until falling_edge(clk);
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rx <= byte(7 downto 6);
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end procedure sendRMII;
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begin
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dv <= '0';
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wait for 35 ns;
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rst <= '0';
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dv <= '0';
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rx <= "00";
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wait for 100 us;
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sendRMII(x"55");
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sendRMII(x"55");
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sendRMII(x"55");
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sendRMII(x"55");
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sendRMII(x"55");
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sendRMII(x"55");
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sendRMII(x"55");
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sendRMII(x"55");
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sendRMII(x"D5");
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sendRMII(x"00");
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sendRMII(x"DE");
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sendRMII(x"AD");
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sendRMII(x"BE");
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sendRMII(x"EF");
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sendRMII(x"00");
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sendRMII(x"01");
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sendRMII(x"02");
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sendRMII(x"03");
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sendRMII(x"04");
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sendRMII(x"05");
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sendRMII(x"06");
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sendRMII(x"01");
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sendRMII(x"02");
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sendRMII(x"AA");
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sendRMII(x"01");
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sendRMII(x"02");
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sendRMII(x"CC");
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sendRMII(x"AA");
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sendRMII(x"55");
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-- Send FCS
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sendRMII(x"BD");
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sendRMII(x"9B");
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sendRMII(x"AC");
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sendRMII(x"54");
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-- sendRMII(x"AB");
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wait until falling_edge(clk);
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wait for 10 ns;
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dv <= '0';
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wait;
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end process sendphy;
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end architecture bench;
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