122 lines
3.0 KiB
VHDL
122 lines
3.0 KiB
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity ws2812bphy is
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generic(
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constant HIGH1 : integer := 40;
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constant LOW1 : integer := 23;
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constant HIGH0 : integer := 20;
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constant LOW0 : integer := 43);
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port(
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clk : in std_logic;
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rst : in std_logic;
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busy : out std_logic;
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ws_out : out std_logic;
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strb : in std_logic;
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red : in unsigned(7 downto 0);
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green : in unsigned(7 downto 0);
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blue : in unsigned(7 downto 0));
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end entity ws2812bphy;
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architecture RTL of ws2812bphy is
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type ws_output_state_t is (IDLE, TRANSMITTING, INTERLEDDELAY);
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signal ws_output_state : ws_output_state_t;
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type bitstate_t is (LOW, HIGH);
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signal bitstate : bitstate_t;
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begin
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ws_output : process(clk, rst) is
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variable counter : integer range 0 to 255 := 0;
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variable color_vector : std_logic_vector(23 downto 0);
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variable bitnum : integer range 0 to 23;
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begin
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if rst = '1' then
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ws_output_state <= IDLE;
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color_vector := (others => '0');
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counter := 0;
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bitstate <= LOW;
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bitnum := 0;
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elsif rising_edge(clk) then
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case ws_output_state is
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when IDLE =>
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bitstate <= LOW;
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if strb = '1' then
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ws_output_state <= TRANSMITTING;
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bitnum := 23;
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color_vector := std_logic_vector(green) & std_logic_vector(red) & std_logic_vector(blue);
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counter := 0;
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bitstate <= HIGH;
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end if;
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when TRANSMITTING =>
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case bitstate is
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when HIGH =>
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if color_vector(bitnum) = '1' then
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if counter < HIGH1 - 1 then
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counter := counter + 1;
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else
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bitstate <= LOW;
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counter := 0;
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end if;
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else
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if counter < HIGH0 -1 then
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counter := counter + 1;
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else
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bitstate <= LOW;
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counter := 0;
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end if;
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end if;
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when LOW =>
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if color_vector(bitnum) = '1' then
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if counter < LOW1 -1 then
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counter := counter + 1;
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else
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bitstate <= HIGH;
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counter := 0;
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if bitnum = 0 then
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ws_output_state <= INTERLEDDELAY;
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counter := 0;
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bitstate <= LOW;
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else
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bitnum := bitnum - 1;
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end if;
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end if;
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else
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if counter < LOW0 - 1 then
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counter := counter + 1;
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else
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bitstate <= HIGH;
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counter := 0;
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if bitnum = 0 then
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ws_output_state <= INTERLEDDELAY;
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counter := 0;
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bitstate <= LOW;
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else
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bitnum := bitnum - 1;
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end if;
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end if;
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end if;
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end case;
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when INTERLEDDELAY =>
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if counter < HIGH1+LOW1+LOW1 then
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counter := counter + 1;
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else
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counter := 0;
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ws_output_state <= IDLE;
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end if;
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end case;
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end if;
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end process ws_output;
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busy <= '0' when ws_output_state = IDLE else '1';
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ws_out <= '1' when bitstate = HIGH else '0';
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end architecture RTL;
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