From 042571053721b732e1adf90e127be1e2915d0440 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Mario=20H=C3=BCttel?= Date: Sat, 7 Apr 2018 19:12:55 +0200 Subject: [PATCH] reset-sync --- top.vhd | 28 +++++++++++++++++++--------- 1 file changed, 19 insertions(+), 9 deletions(-) diff --git a/top.vhd b/top.vhd index 9e27ad8..d2762a4 100644 --- a/top.vhd +++ b/top.vhd @@ -36,9 +36,9 @@ entity top is end entity top; architecture RTL of top is - constant DELAYCNTVAL : integer := 100000; -- set to low value for - -- simulation - constant DEFMAC : std_logic_vector(47 downto 0) := x"00DEADBEEF00"; + constant DELAYCNTVAL : integer := 100000; -- set to low value for + -- simulation + constant DEFMAC : std_logic_vector(47 downto 0) := x"00DEADBEEF00"; type smi_state_t is (IDLE, STROBE); type smi_init_state_t is (SMI_POR, RESET, INIT, DELAY, INIT_COMPLETE); @@ -88,7 +88,17 @@ architecture RTL of top is begin -- architecture RTL - rst <= not rst_hw; + reset_sync : process(clk, rst_hw) is + begin + if rst_hw = '0' then + rst <= '1'; + elsif rising_edge(clk) then + if rst_hw = '1' then + rst <= '0'; + end if; + end if; + end process reset_sync; + smi_1 : entity work.smi generic map ( @@ -198,13 +208,13 @@ begin -- architecture RTL case initstate is when SMI_POR => after_delay_state <= RESET; - delaycounter <= (others => '0'); - initstate <= DELAY; + delaycounter <= (others => '0'); + initstate <= DELAY; when RESET => after_delay_state <= INIT; - delaycounter <= (others => '0'); - sendsmi((others => '0'), x"8000", DELAY); - + delaycounter <= (others => '0'); + sendsmi((others => '0'), x"8000", DELAY); + when DELAY => delaycounter <= delaycounter + 1; if delaycounter = DELAYCNTVAL then -- Set to 100000