init. Works on altera

2018-04-06 17:37:39 +02:00
commit 4f4c36ffe8
9 changed files with 1441 additions and 0 deletions
--- a/bench/test.vhd
+++ b/bench/test.vhd
@@ -0,0 +1,118 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+entity test is
+
+end entity test;
+
+architecture bench of test is
+
+	signal clk  : std_logic;
+	signal rst  : std_logic := '1';
+	signal dv   : std_logic;
+	signal rx   : std_logic_vector(1 downto 0);
+	signal mdc  : std_logic;
+	signal mdio : std_logic;
+	signal led  : std_logic_vector(1 downto 0);
+	signal ws   : std_logic;
+begin  -- architecture bench
+
+
+	top_1 : entity work.top
+		port map (
+			clk    => clk,
+			rst    => rst,
+			mdio   => mdio,
+			mdc    => mdc,
+			rx     => rx,
+			dv     => dv,
+			led1   => led(0),
+			led2   => led(1),
+			ws_out => ws);
+
+
+
+	clkgen : process is
+	begin
+		clk <= '0';
+		wait for 10 ns;
+		clk <= '1';
+		wait for 10 ns;
+	end process clkgen;
+
+
+
+
+
+	sendphy : process is
+		procedure sendRMII(byte : in std_logic_vector(7 downto 0)) is
+		begin
+			wait until falling_edge(clk);
+			dv <= '1';
+			rx <= byte(1 downto 0);
+			wait until falling_edge(clk);
+			rx <= byte(3 downto 2);
+			wait until falling_edge(clk);
+			rx <= byte(5 downto 4);
+			wait until falling_edge(clk);
+			rx <= byte(7 downto 6);
+
+		end procedure sendRMII;
+	begin
+		dv <= '0';
+		
+		wait for 35 ns;
+		rst <= '0';
+		dv  <= '0';
+		rx  <= "00";
+		wait for 100 us;
+		sendRMII(x"55");
+		sendRMII(x"55");
+		sendRMII(x"55");
+		sendRMII(x"55");
+		sendRMII(x"55");
+		sendRMII(x"55");
+		sendRMII(x"55");
+		sendRMII(x"55");
+		sendRMII(x"D5");
+
+		sendRMII(x"00");
+		sendRMII(x"DE");
+		sendRMII(x"AD");
+		sendRMII(x"BE");
+		sendRMII(x"EF");
+		sendRMII(x"00");
+
+		sendRMII(x"01");
+		sendRMII(x"02");
+		sendRMII(x"03");
+		sendRMII(x"04");
+		sendRMII(x"05");
+		sendRMII(x"06");
+
+		sendRMII(x"01");
+		sendRMII(x"02");
+
+		sendRMII(x"AA");
+
+		sendRMII(x"01");
+		sendRMII(x"02");
+
+
+		sendRMII(x"CC");
+		sendRMII(x"AA");
+		sendRMII(x"55");
+		-- Send FCS
+		sendRMII(x"BD");
+		sendRMII(x"9B");
+		sendRMII(x"AC");
+		sendRMII(x"54");
+
+		-- sendRMII(x"AB");
+
+		wait until falling_edge(clk);
+		wait for 10 ns;
+		dv <= '0';
+		wait;
+	end process sendphy;
+end architecture bench;