diff --git a/top.vhd b/top.vhd
index d2762a4..ea9255a 100644
--- a/top.vhd
+++ b/top.vhd
@@ -37,11 +37,12 @@ end entity top;
 
 architecture RTL of top is
 	constant DELAYCNTVAL : integer			     := 100000;	 -- set to low value for
-					-- simulation 
+					-- simulation
+	constant STARTUPDELAY : integer := 50000000;
 	constant DEFMAC	     : std_logic_vector(47 downto 0) := x"00DEADBEEF00";
 
 	type smi_state_t is (IDLE, STROBE);
-	type smi_init_state_t is (SMI_POR, RESET, INIT, DELAY, INIT_COMPLETE);
+	type smi_init_state_t is (SMI_POR, SMI_PORDELAY, RESET, INIT, DELAY, INIT_COMPLETE);
 	type ws_send_t is (WS_READY, WS_SYNC, WS_RED, WS_GREEN, WS_BLUE, WS_PIPE, WS_POST);
 	type receive_t is (PRE, DESTMAC, HEADER, RECV, WAITFORACK);
 
@@ -50,9 +51,8 @@ architecture RTL of top is
 
 	signal sendstate	 : smi_state_t;
 	signal initstate	 : smi_init_state_t := SMI_POR;
-	signal after_delay_state : smi_init_state_t := RESET;
 	signal rst_rxtx		 : std_logic;
-	signal delaycounter	 : unsigned(19 downto 0);
+	signal delaycounter	 : unsigned(26 downto 0);
 	signal smi_reg		 : std_logic_vector(4 downto 0);
 	signal smi_dat		 : std_logic_vector(15 downto 0);
 	signal smi_strb		 : std_logic;
@@ -200,31 +200,35 @@ begin  -- architecture RTL
 			rst_rxtx	  <= '1';
 			initstate	  <= SMI_POR;
 			sendstate	  <= IDLE;
-			after_delay_state <= RESET;
 			delaycounter	  <= (others => '0');
 		elsif rising_edge(clk) then
 			smi_strb <= '0';
 			rst_rxtx <= '1';
 			case initstate is
 				when SMI_POR =>
-					after_delay_state <= RESET;
 					delaycounter	  <= (others => '0');
-					initstate	  <= DELAY;
+					initstate	  <= SMI_PORDELAY;
+				when SMI_PORDELAY =>
+					delaycounter <= delaycounter + 1;
+					if delaycounter = STARTUPDELAY then 
+						initstate <= RESET;
+					end if;
 				when RESET =>
-					after_delay_state <= INIT;
 					delaycounter	  <= (others => '0');
 					sendsmi((others		     => '0'), x"8000", DELAY);
 
 				when DELAY =>
 					delaycounter <= delaycounter + 1;
 					if delaycounter = DELAYCNTVAL then  -- Set to 100000
-						initstate <= after_delay_state;
+						initstate <= INIT;
 					end if;
 				when INIT =>
 					sendsmi((others => '0'), "00" & '1' & '1' & "000" & '1' & "00000000", INIT_COMPLETE);
 				when INIT_COMPLETE =>
 					initstate <= INIT_COMPLETE;
-					rst_rxtx  <= '0';
+					if smi_busy = '0' then
+						rst_rxtx  <= '0';
+						end if;
 			end case;
 		end if;
 	end process initphy;