diff --git a/c/README b/c/README
index 785e6de..06cfd31 100644
--- a/c/README
+++ b/c/README
@@ -1,4 +1,4 @@
-./prog [<mode> <IFNAME>]
+./prog [<mode> <options>]
 
 mode:
 0 is default
@@ -9,7 +9,4 @@ mode:
 3: blue
 4: off
 5: white
-
-IFNAME:
-Interface name like "eth0" or "enp5s0"
-enp5s0 is default
+6: whole string with <options> color 
diff --git a/c/prog.c b/c/prog.c
index e3d534d..80bc396 100644
--- a/c/prog.c
+++ b/c/prog.c
@@ -34,17 +34,14 @@ int main(int argc, char *argv[])
 	int tx_len = 0;
 	int mode;
 	int i;
+	unsigned char r,g,b;
 	char sendbuf[BUF_SIZ];
 	struct ether_header *eh = (struct ether_header *) sendbuf;
 	struct iphdr *iph = (struct iphdr *) (sendbuf + sizeof(struct ether_header));
 	struct sockaddr_ll socket_address;
 	char ifName[IFNAMSIZ];
 	
-	/* Get interface name */
-	if (argc > 2)
-		strcpy(ifName, argv[2]);
-	else
-		strcpy(ifName, DEFAULT_IF);
+	strcpy(ifName, DEFAULT_IF);
 
 	if (argc > 1)
 		mode = atoi(argv[1]);
@@ -349,6 +346,18 @@ sendbuf[tx_len++] = 0x00;
 		for (i = 0; i< 3*60; i++) {
 sendbuf[tx_len++] = 0xff;
 		}
+} else if (mode == 6) {
+	if (argc < 5) return 0;
+	r = (unsigned char) atoi(argv[2]);
+	g = (unsigned char) atoi(argv[3]);
+	b = (unsigned char) atoi(argv[4]);
+	for (i = 0; i< 60; i++) {
+		sendbuf[tx_len++] = r;
+		sendbuf[tx_len++] = g;
+		sendbuf[tx_len++] = b;
+		
+	}
+
 }
 
 
diff --git a/lattice_wrapper.vhd b/lattice_wrapper.vhd
new file mode 100644
index 0000000..299224b
--- /dev/null
+++ b/lattice_wrapper.vhd
@@ -0,0 +1,39 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity lattice_top is
+	
+	port (
+		clk    : in    std_logic;
+		rst    : in    std_logic;
+		mdio   : inout std_logic;
+		mdc    : out   std_logic;
+		dv     : in    std_logic;
+		rx     : in    std_logic_vector(1 downto 0);
+		ws_out : out   std_logic);
+
+end entity lattice_top;
+
+
+architecture RTL of lattice_top is
+signal rst_hw : std_logic;
+begin  -- architecture RTL
+
+rst_hw <= not rst;
+	
+top_1: entity work.top
+	port map (
+		clk	=> clk,
+		rst_hw	=> rst_hw,
+		mdio	=> mdio,
+		mdc	=> mdc,
+		rx	=> rx,
+		dv	=> dv,
+		led1	=> open,
+		led2	=> open,
+		dat_cnt => open,
+		ws_out	=> ws_out);
+	
+
+end architecture RTL;