diff --git a/top.vhd b/top.vhd index 5fec249..6e282fa 100644 --- a/top.vhd +++ b/top.vhd @@ -36,55 +36,58 @@ entity top is end entity top; architecture RTL of top is - constant DELAYCNTVAL : integer := 100000; -- set to low value for + constant DELAYCNTVAL : integer := 100000; -- set to low value for -- simulation - constant STARTUPDELAY : integer := 50000000; - constant DEFMAC : std_logic_vector(47 downto 0) := x"00DEADBEEF00"; + constant STARTUPDELAY : integer := 50000000; + constant DEFMAC : std_logic_vector(47 downto 0) := x"00DEADBEEF00"; + constant PIPE_PKG : std_logic_vector(15 downto 0) := x"AA00"; + constant FIN_PKG : std_logic_vector(15 downto 0) := x"55AA"; type smi_state_t is (IDLE, STROBE); type smi_init_state_t is (SMI_POR, SMI_PORDELAY, RESET, INIT, DELAY, INIT_COMPLETE); type ws_send_t is (WS_READY, WS_SYNC, WS_RED, WS_GREEN, WS_BLUE, WS_PIPE, WS_POST); - type receive_t is (PRE, DESTMAC, HEADER, RECV, WAITFORACK); + type receive_t is (PRE, DESTMAC, SRCMAC, TYPEFIELD, RECV, WAITFORACK); signal rst : std_logic; signal dat_cnt_s : unsigned(3 downto 0); - signal sendstate : smi_state_t; - signal initstate : smi_init_state_t := SMI_POR; - signal rst_rxtx : std_logic; - signal delaycounter : unsigned(26 downto 0); - signal smi_reg : std_logic_vector(4 downto 0); - signal smi_dat : std_logic_vector(15 downto 0); - signal smi_strb : std_logic; - signal smi_busy : std_logic; + signal sendstate : smi_state_t; + signal initstate : smi_init_state_t := SMI_POR; + signal rst_rxtx : std_logic; + signal delaycounter : unsigned(26 downto 0); + signal smi_reg : std_logic_vector(4 downto 0); + signal smi_dat : std_logic_vector(15 downto 0); + signal smi_strb : std_logic; + signal smi_busy : std_logic; --- - signal sof : std_logic; - signal eof : std_logic; - signal eth_dat : std_logic_vector(7 downto 0); - signal eth_strb : std_logic; - signal crc_valid : std_logic; + signal sof : std_logic; + signal eof : std_logic; + signal eth_dat : std_logic_vector(7 downto 0); + signal eth_strb : std_logic; + signal crc_valid : std_logic; -- - signal fifo_in : std_logic_vector(7 downto 0); - signal fifo_out : std_logic_vector(7 downto 0); - signal fifo_wr : std_logic; - signal fifo_rd : std_logic; - signal fifo_rst : std_logic; - signal fifo_full : std_logic; - signal fifo_empty : std_logic; + signal fifo_in : std_logic_vector(7 downto 0); + signal fifo_out : std_logic_vector(7 downto 0); + signal fifo_wr : std_logic; + signal fifo_rd : std_logic; + signal fifo_rst : std_logic; + signal fifo_full : std_logic; + signal fifo_empty : std_logic; -- - signal fifo_data_avail : std_logic; - signal fifo_data_ack : std_logic; - signal recv_state : receive_t; - signal mac : std_logic_vector(47 downto 0); - signal recv_cnt : integer range 0 to 15; + signal fifo_data_avail : std_logic; + signal fifo_data_ack : std_logic; + signal recv_state : receive_t; + signal mac : std_logic_vector(47 downto 0); + signal recv_cnt : integer range 0 to 15; + signal pkg_type : std_logic_vector(15 downto 0); -- - signal ws_busy : std_logic; - signal ws_strb : std_logic; - signal red : unsigned(7 downto 0); - signal green : unsigned(7 downto 0); - signal blue : unsigned(7 downto 0); + signal ws_busy : std_logic; + signal ws_strb : std_logic; + signal red : unsigned(7 downto 0); + signal green : unsigned(7 downto 0); + signal blue : unsigned(7 downto 0); -- - signal ws_state : ws_send_t; + signal ws_state : ws_send_t; begin -- architecture RTL @@ -194,28 +197,28 @@ begin -- architecture RTL begin if rst = '1' then - smi_reg <= (others => '0'); - smi_dat <= (others => '0'); - smi_strb <= '0'; - rst_rxtx <= '1'; - initstate <= SMI_POR; - sendstate <= IDLE; - delaycounter <= (others => '0'); + smi_reg <= (others => '0'); + smi_dat <= (others => '0'); + smi_strb <= '0'; + rst_rxtx <= '1'; + initstate <= SMI_POR; + sendstate <= IDLE; + delaycounter <= (others => '0'); elsif rising_edge(clk) then smi_strb <= '0'; rst_rxtx <= '1'; case initstate is when SMI_POR => - delaycounter <= (others => '0'); - initstate <= SMI_PORDELAY; + delaycounter <= (others => '0'); + initstate <= SMI_PORDELAY; when SMI_PORDELAY => delaycounter <= delaycounter + 1; - if delaycounter = STARTUPDELAY then + if delaycounter = STARTUPDELAY then initstate <= RESET; end if; when RESET => - delaycounter <= (others => '0'); - sendsmi((others => '0'), x"8000", DELAY); + delaycounter <= (others => '0'); + sendsmi((others => '0'), x"8000", DELAY); when DELAY => delaycounter <= delaycounter + 1; @@ -227,8 +230,8 @@ begin -- architecture RTL when INIT_COMPLETE => initstate <= INIT_COMPLETE; if smi_busy = '0' then - rst_rxtx <= '0'; - end if; + rst_rxtx <= '0'; + end if; end case; end if; end process initphy; @@ -246,6 +249,7 @@ begin -- architecture RTL led1 <= '1'; led2 <= '1'; recv_cnt <= 0; + pkg_type <= (others => '0'); mac <= (others => '0'); elsif rising_edge(clk) then -- rising clock edge fifo_rst <= '0'; @@ -254,6 +258,7 @@ begin -- architecture RTL when PRE => if sof = '1' then recv_cnt <= 0; + pkg_type <= (others => '0'); mac <= (others => '0'); recv_state <= DESTMAC; led1 <= '1'; @@ -266,28 +271,35 @@ begin -- architecture RTL elsif eth_strb = '1' then recv_cnt <= recv_cnt + 1; mac <= mac(39 downto 0) & eth_dat; - if recv_cnt = 5 then + if recv_cnt = 5 and (mac(39 downto 0) & eth_dat) = DEFMAC then recv_cnt <= 0; - recv_state <= HEADER; + recv_state <= SRCMAC; end if; end if; - when HEADER => - led1 <= '0'; + when SRCMAC => if eof = '1' then recv_state <= PRE; elsif eth_strb = '1' then recv_cnt <= recv_cnt + 1; - if recv_cnt = 7 then - if mac = DEFMAC then - recv_state <= RECV; - dat_cnt_s <= (others => '0'); - else - recv_state <= PRE; - - end if; + if recv_cnt 5 then -- SRC_MAC received + recv_state <= TYPEFIELD + recv_cnt <= 0; end if; end if; + + when TYPEFIELD => + if eof = '1' then + recv_state <= PRE; + elsif eth_strb = '1' then + recv_cnt <= recv_cnt + 1; + pkg_type <= pkg_type(7 downto 0) & eth_dat; + if recv_cnt = 1 then -- Type received + recv_cnt <= 0; + recv_state <= RECV; + end if; + end if; + when RECV => led2 <= '0'; if eth_strb = '1' and fifo_full /= '1' then