edited testbench

bench/test.vhd

@@ -7,29 +7,31 @@ end entity test;
 
 architecture bench of test is
 
-	signal clk  : std_logic;
+	signal clk     : std_logic;
-	signal rst  : std_logic := '1';
+	signal rst     : std_logic := '1';
-	signal dv   : std_logic;
+	signal dv      : std_logic;
-	signal rx   : std_logic_vector(1 downto 0);
+	signal rx      : std_logic_vector(1 downto 0);
-	signal mdc  : std_logic;
+	signal mdc     : std_logic;
-	signal mdio : std_logic;
+	signal mdio    : std_logic;
-	signal led  : std_logic_vector(1 downto 0);
+	signal led     : std_logic_vector(1 downto 0);
-	signal ws   : std_logic;
+	signal ws      : std_logic;
+	signal rst_hw  : std_logic;
+	signal dat_cnt : std_logic_vector(3 downto 0);
 begin  -- architecture bench
 
 
 	top_1 : entity work.top
 		port map (
-			clk    => clk,
+			clk	=> clk,
-			rst    => rst,
+			rst_hw	=> rst_hw,
-			mdio   => mdio,
+			mdio	=> mdio,
-			mdc    => mdc,
+			mdc	=> mdc,
-			rx     => rx,
+			rx	=> rx,
-			dv     => dv,
+			dv	=> dv,
-			led1   => led(0),
+			led1	=> led(0),
-			led2   => led(1),
+			led2	=> led(1),
-			ws_out => ws);
+			dat_cnt => dat_cnt,
-
+			ws_out	=> ws);
 
 
 	clkgen : process is
@@ -41,7 +43,7 @@ begin  -- architecture bench
 	end process clkgen;
 
 
-
+	rst_hw <= not rst;
 
 
 	sendphy : process is
@@ -60,7 +62,7 @@ begin  -- architecture bench
 		end procedure sendRMII;
 	begin
 		dv <= '0';
-		
+
 		wait for 35 ns;
 		rst <= '0';
 		dv  <= '0';
@@ -94,7 +96,6 @@ begin  -- architecture bench
 		sendRMII(x"02");
 
 		sendRMII(x"AA");
-
 		sendRMII(x"01");
 		sendRMII(x"02");
 
@@ -103,10 +104,10 @@ begin  -- architecture bench
 		sendRMII(x"AA");
 		sendRMII(x"55");
 		-- Send FCS
-		sendRMII(x"BD");
+		sendRMII(x"2B");
-		sendRMII(x"9B");
+		sendRMII(x"69");
-		sendRMII(x"AC");
+		sendRMII(x"4E");
-		sendRMII(x"54");
+		sendRMII(x"A8");
 
 		-- sendRMII(x"AB");