fpga/ws2812b-eth
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edited testbench

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This commit is contained in:
Mario Hüttel 2018-04-07 18:44:51 +02:00
parent 75c50b63c1
commit 9dd10afae1
1 changed files with 26 additions and 25 deletions
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17
bench/test.vhd
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@ -15,23 +15,25 @@ architecture bench of test is
signal mdio : std_logic;
signal led : std_logic_vector(1 downto 0);
signal ws : std_logic;
signal rst_hw : std_logic;
signal dat_cnt : std_logic_vector(3 downto 0);
begin -- architecture bench
top_1 : entity work.top
port map (
clk => clk,
rst => rst,
rst_hw => rst_hw,
mdio => mdio,
mdc => mdc,
rx => rx,
dv => dv,
led1 => led(0),
led2 => led(1),
dat_cnt => dat_cnt,
ws_out => ws);
clkgen : process is
begin
clk <= '0';
@ -41,7 +43,7 @@ begin -- architecture bench
end process clkgen;
rst_hw <= not rst;
sendphy : process is
@ -94,7 +96,6 @@ begin -- architecture bench
sendRMII(x"02");
sendRMII(x"AA");
sendRMII(x"01");
sendRMII(x"02");
@ -103,10 +104,10 @@ begin -- architecture bench
sendRMII(x"AA");
sendRMII(x"55");
-- Send FCS
sendRMII(x"BD");
sendRMII(x"9B");
sendRMII(x"AC");
sendRMII(x"54");
sendRMII(x"2B");
sendRMII(x"69");
sendRMII(x"4E");
sendRMII(x"A8");
-- sendRMII(x"AB");