From c909e0c7030ef98a6c130c17e6f8edaa09d3ca24 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Mario=20H=C3=BCttel?= Date: Sat, 7 Apr 2018 19:09:27 +0200 Subject: [PATCH] edited simulation files --- bench/test.vhd | 10 ++--- top.vhd | 112 +++++++++++++++++++++++++++---------------------- 2 files changed, 66 insertions(+), 56 deletions(-) diff --git a/bench/test.vhd b/bench/test.vhd index 62d7e1a..8f94ae4 100644 --- a/bench/test.vhd +++ b/bench/test.vhd @@ -67,7 +67,7 @@ begin -- architecture bench rst <= '0'; dv <= '0'; rx <= "00"; - wait for 100 us; + wait for 350 us; sendRMII(x"55"); sendRMII(x"55"); sendRMII(x"55"); @@ -104,10 +104,10 @@ begin -- architecture bench sendRMII(x"AA"); sendRMII(x"55"); -- Send FCS - sendRMII(x"2B"); - sendRMII(x"69"); - sendRMII(x"4E"); - sendRMII(x"A8"); + sendRMII(x"3A"); + sendRMII(x"97"); + sendRMII(x"D9"); + sendRMII(x"7A"); -- sendRMII(x"AB"); diff --git a/top.vhd b/top.vhd index 9b08c6d..9e27ad8 100644 --- a/top.vhd +++ b/top.vhd @@ -6,7 +6,7 @@ -- Author : Mario Hüttel -- Company : -- Created : 2018-04-05 --- Last update: 2018-04-06 +-- Last update: 2018-04-07 -- Platform : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- @@ -36,53 +36,55 @@ entity top is end entity top; architecture RTL of top is - constant DELAYCNTVAL : integer := 100000; - constant DEFMAC : std_logic_vector(47 downto 0) := x"00DEADBEEF00"; + constant DELAYCNTVAL : integer := 100000; -- set to low value for + -- simulation + constant DEFMAC : std_logic_vector(47 downto 0) := x"00DEADBEEF00"; type smi_state_t is (IDLE, STROBE); - type smi_init_state_t is (RESET, INIT, DELAY, INIT_COMPLETE); + type smi_init_state_t is (SMI_POR, RESET, INIT, DELAY, INIT_COMPLETE); type ws_send_t is (WS_READY, WS_SYNC, WS_RED, WS_GREEN, WS_BLUE, WS_PIPE, WS_POST); type receive_t is (PRE, DESTMAC, HEADER, RECV, WAITFORACK); - signal rst : std_logic; + signal rst : std_logic; signal dat_cnt_s : unsigned(3 downto 0); - signal sendstate : smi_state_t; - signal initstate : smi_init_state_t := RESET; - signal rst_rxtx : std_logic; - signal delaycounter : unsigned(19 downto 0); - signal smi_reg : std_logic_vector(4 downto 0); - signal smi_dat : std_logic_vector(15 downto 0); - signal smi_strb : std_logic; - signal smi_busy : std_logic; + signal sendstate : smi_state_t; + signal initstate : smi_init_state_t := SMI_POR; + signal after_delay_state : smi_init_state_t := RESET; + signal rst_rxtx : std_logic; + signal delaycounter : unsigned(19 downto 0); + signal smi_reg : std_logic_vector(4 downto 0); + signal smi_dat : std_logic_vector(15 downto 0); + signal smi_strb : std_logic; + signal smi_busy : std_logic; --- - signal sof : std_logic; - signal eof : std_logic; - signal eth_dat : std_logic_vector(7 downto 0); - signal eth_strb : std_logic; - signal crc_valid : std_logic; + signal sof : std_logic; + signal eof : std_logic; + signal eth_dat : std_logic_vector(7 downto 0); + signal eth_strb : std_logic; + signal crc_valid : std_logic; -- - signal fifo_in : std_logic_vector(7 downto 0); - signal fifo_out : std_logic_vector(7 downto 0); - signal fifo_wr : std_logic; - signal fifo_rd : std_logic; - signal fifo_rst : std_logic; - signal fifo_full : std_logic; - signal fifo_empty : std_logic; + signal fifo_in : std_logic_vector(7 downto 0); + signal fifo_out : std_logic_vector(7 downto 0); + signal fifo_wr : std_logic; + signal fifo_rd : std_logic; + signal fifo_rst : std_logic; + signal fifo_full : std_logic; + signal fifo_empty : std_logic; -- - signal fifo_data_avail : std_logic; - signal fifo_data_ack : std_logic; - signal recv_state : receive_t; - signal mac : std_logic_vector(47 downto 0); - signal recv_cnt : integer range 0 to 15; + signal fifo_data_avail : std_logic; + signal fifo_data_ack : std_logic; + signal recv_state : receive_t; + signal mac : std_logic_vector(47 downto 0); + signal recv_cnt : integer range 0 to 15; -- - signal ws_busy : std_logic; - signal ws_strb : std_logic; - signal red : unsigned(7 downto 0); - signal green : unsigned(7 downto 0); - signal blue : unsigned(7 downto 0); + signal ws_busy : std_logic; + signal ws_strb : std_logic; + signal red : unsigned(7 downto 0); + signal green : unsigned(7 downto 0); + signal blue : unsigned(7 downto 0); -- - signal ws_state : ws_send_t; + signal ws_state : ws_send_t; begin -- architecture RTL @@ -182,23 +184,31 @@ begin -- architecture RTL begin if rst = '1' then - smi_reg <= (others => '0'); - smi_dat <= (others => '0'); - smi_strb <= '0'; - rst_rxtx <= '1'; - initstate <= RESET; - sendstate <= IDLE; - delaycounter <= (others => '0'); + smi_reg <= (others => '0'); + smi_dat <= (others => '0'); + smi_strb <= '0'; + rst_rxtx <= '1'; + initstate <= SMI_POR; + sendstate <= IDLE; + after_delay_state <= RESET; + delaycounter <= (others => '0'); elsif rising_edge(clk) then smi_strb <= '0'; rst_rxtx <= '1'; case initstate is + when SMI_POR => + after_delay_state <= RESET; + delaycounter <= (others => '0'); + initstate <= DELAY; when RESET => + after_delay_state <= INIT; + delaycounter <= (others => '0'); sendsmi((others => '0'), x"8000", DELAY); + when DELAY => delaycounter <= delaycounter + 1; if delaycounter = DELAYCNTVAL then -- Set to 100000 - initstate <= INIT; + initstate <= after_delay_state; end if; when INIT => sendsmi((others => '0'), "00" & '1' & '1' & "000" & '1' & "00000000", INIT_COMPLETE); @@ -218,9 +228,9 @@ begin -- architecture RTL fifo_in <= (others => '0'); fifo_data_avail <= '0'; recv_state <= PRE; - dat_cnt_s <= (others => '0'); - led1 <= '1'; - led2 <= '1'; + dat_cnt_s <= (others => '0'); + led1 <= '1'; + led2 <= '1'; recv_cnt <= 0; mac <= (others => '0'); elsif rising_edge(clk) then -- rising clock edge @@ -257,7 +267,7 @@ begin -- architecture RTL if recv_cnt = 7 then if mac = DEFMAC then recv_state <= RECV; - dat_cnt_s <= (others =>'0'); + dat_cnt_s <= (others => '0'); else recv_state <= PRE; @@ -267,12 +277,12 @@ begin -- architecture RTL when RECV => led2 <= '0'; if eth_strb = '1' and fifo_full /= '1' then - fifo_in <= eth_dat; - fifo_wr <= '1'; + fifo_in <= eth_dat; + fifo_wr <= '1'; dat_cnt_s <= dat_cnt_s +1; end if; if eof = '1' then - if crc_valid = '1' then-- or crc_valid = '0' then + if crc_valid = '1' then -- or crc_valid = '0' then recv_state <= WAITFORACK; fifo_data_avail <= '1'; --led2 <= '0';