From ee5da6812c5071cc88f031f68f704f346eeaed0f Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Mario=20H=C3=BCttel?= <mario.huettel@gmx.net>
Date: Fri, 13 Apr 2018 21:35:44 +0200
Subject: [PATCH] implemented

---
 top.vhd | 19 +++++++++++++------
 1 file changed, 13 insertions(+), 6 deletions(-)

diff --git a/top.vhd b/top.vhd
index 6e282fa..f73b8cb 100644
--- a/top.vhd
+++ b/top.vhd
@@ -308,12 +308,19 @@ begin  -- architecture RTL
 						dat_cnt_s <= dat_cnt_s +1;
 					end if;
 					if eof = '1' then
-						if crc_valid = '1' then	 -- or crc_valid = '0' then
-							recv_state	<= WAITFORACK;
-							fifo_data_avail <= '1';
-					--led2 <= '0';
-						else
-					--led2 <= '1';
+						if crc_valid = '1' then
+							if pkg_type = PIPE_PKG then
+					-- Wait for further frames
+					-- This is also called with any
+					-- undefined TYPEFIELD
+								recv_state <= PRE;
+							elsif pkg_type = FIN_PKG then
+								fifo_data_avail <= '1';
+								recv_state	<= WAITFORACK;
+							else
+								recv_state <= PRE;
+							end if;
+						else  -- Eth Frame invalid. Discard
 							fifo_rst   <= '1';
 							recv_state <= PRE;
 						end if;