fpga/ws2812b-eth
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1 changed files with 67 additions and 86 deletions
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top.vhd
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@ -40,13 +40,11 @@ architecture RTL of top is
-- simulation
constant STARTUPDELAY : integer := 50000000;
constant DEFMAC : std_logic_vector(47 downto 0) := x"00DEADBEEF00";
constant PIPE_PKG : std_logic_vector(15 downto 0) := x"AA00";
constant FIN_PKG : std_logic_vector(15 downto 0) := x"55AA";
type smi_state_t is (IDLE, STROBE);
type smi_init_state_t is (SMI_POR, SMI_PORDELAY, RESET, INIT, DELAY, INIT_COMPLETE);
type ws_send_t is (WS_READY, WS_SYNC, WS_RED, WS_GREEN, WS_BLUE, WS_PIPE, WS_POST);
type receive_t is (PRE, DESTMAC, SRCMAC, TYPEFIELD, RECV, WAITFORACK);
type receive_t is (PRE, DESTMAC, HEADER, RECV, WAITFORACK);
signal rst : std_logic;
signal dat_cnt_s : unsigned(3 downto 0);
@ -79,7 +77,6 @@ architecture RTL of top is
signal recv_state : receive_t;
signal mac : std_logic_vector(47 downto 0);
signal recv_cnt : integer range 0 to 15;
signal pkg_type : std_logic_vector(15 downto 0);
--
signal ws_busy : std_logic;
signal ws_strb : std_logic;
@ -249,7 +246,6 @@ begin -- architecture RTL
led1 <= '1';
led2 <= '1';
recv_cnt <= 0;
pkg_type <= (others => '0');
mac <= (others => '0');
elsif rising_edge(clk) then -- rising clock edge
fifo_rst <= '0';
@ -258,7 +254,6 @@ begin -- architecture RTL
when PRE =>
if sof = '1' then
recv_cnt <= 0;
pkg_type <= (others => '0');
mac <= (others => '0');
recv_state <= DESTMAC;
led1 <= '1';
@ -271,35 +266,28 @@ begin -- architecture RTL
elsif eth_strb = '1' then
recv_cnt <= recv_cnt + 1;
mac <= mac(39 downto 0) & eth_dat;
if recv_cnt = 5 and (mac(39 downto 0) & eth_dat) = DEFMAC then
if recv_cnt = 5 then
recv_cnt <= 0;
recv_state <= SRCMAC;
recv_state <= HEADER;
end if;
end if;
when SRCMAC =>
when HEADER =>
led1 <= '0';
if eof = '1' then
recv_state <= PRE;
elsif eth_strb = '1' then
recv_cnt <= recv_cnt + 1;
if recv_cnt 5 then -- SRC_MAC received
recv_state <= TYPEFIELD
recv_cnt <= 0;
end if;
end if;
when TYPEFIELD =>
if eof = '1' then
recv_state <= PRE;
elsif eth_strb = '1' then
recv_cnt <= recv_cnt + 1;
pkg_type <= pkg_type(7 downto 0) & eth_dat;
if recv_cnt = 1 then -- Type received
recv_cnt <= 0;
if recv_cnt = 7 then
if mac = DEFMAC then
recv_state <= RECV;
end if;
end if;
dat_cnt_s <= (others => '0');
else
recv_state <= PRE;
end if;
end if;
end if;
when RECV =>
led2 <= '0';
if eth_strb = '1' and fifo_full /= '1' then
@ -308,19 +296,12 @@ begin -- architecture RTL
dat_cnt_s <= dat_cnt_s +1;
end if;
if eof = '1' then
if crc_valid = '1' then
if pkg_type = PIPE_PKG then
-- Wait for further frames
-- This is also called with any
-- undefined TYPEFIELD
recv_state <= PRE;
elsif pkg_type = FIN_PKG then
fifo_data_avail <= '1';
if crc_valid = '1' then -- or crc_valid = '0' then
recv_state <= WAITFORACK;
fifo_data_avail <= '1';
--led2 <= '0';
else
recv_state <= PRE;
end if;
else -- Eth Frame invalid. Discard
--led2 <= '1';
fifo_rst <= '1';
recv_state <= PRE;
end if;