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top.vhd
151
top.vhd
@ -36,58 +36,55 @@ entity top is
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end entity top;
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architecture RTL of top is
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constant DELAYCNTVAL : integer := 100000; -- set to low value for
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constant DELAYCNTVAL : integer := 100000; -- set to low value for
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-- simulation
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constant STARTUPDELAY : integer := 50000000;
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constant DEFMAC : std_logic_vector(47 downto 0) := x"00DEADBEEF00";
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constant PIPE_PKG : std_logic_vector(15 downto 0) := x"AA00";
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constant FIN_PKG : std_logic_vector(15 downto 0) := x"55AA";
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constant STARTUPDELAY : integer := 50000000;
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constant DEFMAC : std_logic_vector(47 downto 0) := x"00DEADBEEF00";
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type smi_state_t is (IDLE, STROBE);
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type smi_init_state_t is (SMI_POR, SMI_PORDELAY, RESET, INIT, DELAY, INIT_COMPLETE);
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type ws_send_t is (WS_READY, WS_SYNC, WS_RED, WS_GREEN, WS_BLUE, WS_PIPE, WS_POST);
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type receive_t is (PRE, DESTMAC, SRCMAC, TYPEFIELD, RECV, WAITFORACK);
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type receive_t is (PRE, DESTMAC, HEADER, RECV, WAITFORACK);
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signal rst : std_logic;
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signal dat_cnt_s : unsigned(3 downto 0);
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signal sendstate : smi_state_t;
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signal initstate : smi_init_state_t := SMI_POR;
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signal rst_rxtx : std_logic;
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signal delaycounter : unsigned(26 downto 0);
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signal smi_reg : std_logic_vector(4 downto 0);
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signal smi_dat : std_logic_vector(15 downto 0);
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signal smi_strb : std_logic;
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signal smi_busy : std_logic;
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signal sendstate : smi_state_t;
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signal initstate : smi_init_state_t := SMI_POR;
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signal rst_rxtx : std_logic;
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signal delaycounter : unsigned(26 downto 0);
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signal smi_reg : std_logic_vector(4 downto 0);
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signal smi_dat : std_logic_vector(15 downto 0);
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signal smi_strb : std_logic;
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signal smi_busy : std_logic;
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---
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signal sof : std_logic;
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signal eof : std_logic;
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signal eth_dat : std_logic_vector(7 downto 0);
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signal eth_strb : std_logic;
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signal crc_valid : std_logic;
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signal sof : std_logic;
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signal eof : std_logic;
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signal eth_dat : std_logic_vector(7 downto 0);
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signal eth_strb : std_logic;
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signal crc_valid : std_logic;
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--
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signal fifo_in : std_logic_vector(7 downto 0);
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signal fifo_out : std_logic_vector(7 downto 0);
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signal fifo_wr : std_logic;
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signal fifo_rd : std_logic;
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signal fifo_rst : std_logic;
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signal fifo_full : std_logic;
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signal fifo_empty : std_logic;
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signal fifo_in : std_logic_vector(7 downto 0);
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signal fifo_out : std_logic_vector(7 downto 0);
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signal fifo_wr : std_logic;
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signal fifo_rd : std_logic;
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signal fifo_rst : std_logic;
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signal fifo_full : std_logic;
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signal fifo_empty : std_logic;
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--
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signal fifo_data_avail : std_logic;
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signal fifo_data_ack : std_logic;
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signal recv_state : receive_t;
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signal mac : std_logic_vector(47 downto 0);
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signal recv_cnt : integer range 0 to 15;
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signal pkg_type : std_logic_vector(15 downto 0);
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signal fifo_data_avail : std_logic;
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signal fifo_data_ack : std_logic;
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signal recv_state : receive_t;
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signal mac : std_logic_vector(47 downto 0);
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signal recv_cnt : integer range 0 to 15;
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--
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signal ws_busy : std_logic;
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signal ws_strb : std_logic;
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signal red : unsigned(7 downto 0);
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signal green : unsigned(7 downto 0);
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signal blue : unsigned(7 downto 0);
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signal ws_busy : std_logic;
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signal ws_strb : std_logic;
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signal red : unsigned(7 downto 0);
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signal green : unsigned(7 downto 0);
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signal blue : unsigned(7 downto 0);
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--
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signal ws_state : ws_send_t;
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signal ws_state : ws_send_t;
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begin -- architecture RTL
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@ -197,28 +194,28 @@ begin -- architecture RTL
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begin
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if rst = '1' then
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smi_reg <= (others => '0');
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smi_dat <= (others => '0');
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smi_strb <= '0';
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rst_rxtx <= '1';
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initstate <= SMI_POR;
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sendstate <= IDLE;
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delaycounter <= (others => '0');
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smi_reg <= (others => '0');
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smi_dat <= (others => '0');
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smi_strb <= '0';
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rst_rxtx <= '1';
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initstate <= SMI_POR;
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sendstate <= IDLE;
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delaycounter <= (others => '0');
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elsif rising_edge(clk) then
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smi_strb <= '0';
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rst_rxtx <= '1';
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case initstate is
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when SMI_POR =>
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delaycounter <= (others => '0');
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initstate <= SMI_PORDELAY;
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delaycounter <= (others => '0');
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initstate <= SMI_PORDELAY;
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when SMI_PORDELAY =>
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delaycounter <= delaycounter + 1;
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if delaycounter = STARTUPDELAY then
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initstate <= RESET;
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end if;
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when RESET =>
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delaycounter <= (others => '0');
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sendsmi((others => '0'), x"8000", DELAY);
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delaycounter <= (others => '0');
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sendsmi((others => '0'), x"8000", DELAY);
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when DELAY =>
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delaycounter <= delaycounter + 1;
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@ -230,8 +227,8 @@ begin -- architecture RTL
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when INIT_COMPLETE =>
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initstate <= INIT_COMPLETE;
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if smi_busy = '0' then
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rst_rxtx <= '0';
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end if;
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rst_rxtx <= '0';
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end if;
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end case;
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end if;
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end process initphy;
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@ -249,7 +246,6 @@ begin -- architecture RTL
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led1 <= '1';
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led2 <= '1';
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recv_cnt <= 0;
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pkg_type <= (others => '0');
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mac <= (others => '0');
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elsif rising_edge(clk) then -- rising clock edge
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fifo_rst <= '0';
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@ -258,7 +254,6 @@ begin -- architecture RTL
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when PRE =>
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if sof = '1' then
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recv_cnt <= 0;
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pkg_type <= (others => '0');
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mac <= (others => '0');
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recv_state <= DESTMAC;
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led1 <= '1';
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@ -271,35 +266,28 @@ begin -- architecture RTL
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elsif eth_strb = '1' then
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recv_cnt <= recv_cnt + 1;
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mac <= mac(39 downto 0) & eth_dat;
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if recv_cnt = 5 and (mac(39 downto 0) & eth_dat) = DEFMAC then
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if recv_cnt = 5 then
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recv_cnt <= 0;
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recv_state <= SRCMAC;
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recv_state <= HEADER;
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end if;
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end if;
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when SRCMAC =>
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when HEADER =>
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led1 <= '0';
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if eof = '1' then
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recv_state <= PRE;
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elsif eth_strb = '1' then
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recv_cnt <= recv_cnt + 1;
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if recv_cnt 5 then -- SRC_MAC received
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recv_state <= TYPEFIELD
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recv_cnt <= 0;
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if recv_cnt = 7 then
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if mac = DEFMAC then
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recv_state <= RECV;
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dat_cnt_s <= (others => '0');
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else
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recv_state <= PRE;
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end if;
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end if;
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end if;
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when TYPEFIELD =>
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if eof = '1' then
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recv_state <= PRE;
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elsif eth_strb = '1' then
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recv_cnt <= recv_cnt + 1;
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pkg_type <= pkg_type(7 downto 0) & eth_dat;
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if recv_cnt = 1 then -- Type received
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recv_cnt <= 0;
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recv_state <= RECV;
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end if;
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end if;
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when RECV =>
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led2 <= '0';
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if eth_strb = '1' and fifo_full /= '1' then
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@ -308,19 +296,12 @@ begin -- architecture RTL
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dat_cnt_s <= dat_cnt_s +1;
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end if;
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if eof = '1' then
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if crc_valid = '1' then
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if pkg_type = PIPE_PKG then
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-- Wait for further frames
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-- This is also called with any
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-- undefined TYPEFIELD
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recv_state <= PRE;
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elsif pkg_type = FIN_PKG then
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fifo_data_avail <= '1';
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recv_state <= WAITFORACK;
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else
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recv_state <= PRE;
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end if;
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else -- Eth Frame invalid. Discard
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if crc_valid = '1' then -- or crc_valid = '0' then
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recv_state <= WAITFORACK;
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fifo_data_avail <= '1';
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--led2 <= '0';
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else
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--led2 <= '1';
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fifo_rst <= '1';
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recv_state <= PRE;
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end if;
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