fpga/ws2812b-eth
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merge into: fpga:master
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fpga:dev-multipack
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pull from: fpga:dev-multipack
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fpga:dev-multipack
fpga:master

2 Commits
master ... dev-multip

Author SHA1 Message Date
Mario Hüttel
ee5da6812c implemented 2018-04-13 21:35:44 +02:00
Mario Hüttel
763edd1900 read in type field 2018-04-13 21:28:02 +02:00
1 changed files with 86 additions and 67 deletions
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153
top.vhd
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@ -36,55 +36,58 @@ entity top is
end entity top; end entity top;
architecture RTL of top is architecture RTL of top is
constant DELAYCNTVAL : integer := 100000; -- set to low value for constant DELAYCNTVAL : integer := 100000; -- set to low value for
-- simulation -- simulation
constant STARTUPDELAY : integer := 50000000; constant STARTUPDELAY : integer := 50000000;
constant DEFMAC : std_logic_vector(47 downto 0) := x"00DEADBEEF00"; constant DEFMAC : std_logic_vector(47 downto 0) := x"00DEADBEEF00";
constant PIPE_PKG : std_logic_vector(15 downto 0) := x"AA00";
constant FIN_PKG : std_logic_vector(15 downto 0) := x"55AA";
type smi_state_t is (IDLE, STROBE); type smi_state_t is (IDLE, STROBE);
type smi_init_state_t is (SMI_POR, SMI_PORDELAY, RESET, INIT, DELAY, INIT_COMPLETE); type smi_init_state_t is (SMI_POR, SMI_PORDELAY, RESET, INIT, DELAY, INIT_COMPLETE);
type ws_send_t is (WS_READY, WS_SYNC, WS_RED, WS_GREEN, WS_BLUE, WS_PIPE, WS_POST); type ws_send_t is (WS_READY, WS_SYNC, WS_RED, WS_GREEN, WS_BLUE, WS_PIPE, WS_POST);
type receive_t is (PRE, DESTMAC, HEADER, RECV, WAITFORACK); type receive_t is (PRE, DESTMAC, SRCMAC, TYPEFIELD, RECV, WAITFORACK);
signal rst : std_logic; signal rst : std_logic;
signal dat_cnt_s : unsigned(3 downto 0); signal dat_cnt_s : unsigned(3 downto 0);
signal sendstate : smi_state_t; signal sendstate : smi_state_t;
signal initstate : smi_init_state_t := SMI_POR; signal initstate : smi_init_state_t := SMI_POR;
signal rst_rxtx : std_logic; signal rst_rxtx : std_logic;
signal delaycounter : unsigned(26 downto 0); signal delaycounter : unsigned(26 downto 0);
signal smi_reg : std_logic_vector(4 downto 0); signal smi_reg : std_logic_vector(4 downto 0);
signal smi_dat : std_logic_vector(15 downto 0); signal smi_dat : std_logic_vector(15 downto 0);
signal smi_strb : std_logic; signal smi_strb : std_logic;
signal smi_busy : std_logic; signal smi_busy : std_logic;
--- ---
signal sof : std_logic; signal sof : std_logic;
signal eof : std_logic; signal eof : std_logic;
signal eth_dat : std_logic_vector(7 downto 0); signal eth_dat : std_logic_vector(7 downto 0);
signal eth_strb : std_logic; signal eth_strb : std_logic;
signal crc_valid : std_logic; signal crc_valid : std_logic;
-- --
signal fifo_in : std_logic_vector(7 downto 0); signal fifo_in : std_logic_vector(7 downto 0);
signal fifo_out : std_logic_vector(7 downto 0); signal fifo_out : std_logic_vector(7 downto 0);
signal fifo_wr : std_logic; signal fifo_wr : std_logic;
signal fifo_rd : std_logic; signal fifo_rd : std_logic;
signal fifo_rst : std_logic; signal fifo_rst : std_logic;
signal fifo_full : std_logic; signal fifo_full : std_logic;
signal fifo_empty : std_logic; signal fifo_empty : std_logic;
-- --
signal fifo_data_avail : std_logic; signal fifo_data_avail : std_logic;
signal fifo_data_ack : std_logic; signal fifo_data_ack : std_logic;
signal recv_state : receive_t; signal recv_state : receive_t;
signal mac : std_logic_vector(47 downto 0); signal mac : std_logic_vector(47 downto 0);
signal recv_cnt : integer range 0 to 15; signal recv_cnt : integer range 0 to 15;
signal pkg_type : std_logic_vector(15 downto 0);
-- --
signal ws_busy : std_logic; signal ws_busy : std_logic;
signal ws_strb : std_logic; signal ws_strb : std_logic;
signal red : unsigned(7 downto 0); signal red : unsigned(7 downto 0);
signal green : unsigned(7 downto 0); signal green : unsigned(7 downto 0);
signal blue : unsigned(7 downto 0); signal blue : unsigned(7 downto 0);
-- --
signal ws_state : ws_send_t; signal ws_state : ws_send_t;
begin -- architecture RTL begin -- architecture RTL
@ -194,28 +197,28 @@ begin -- architecture RTL
begin begin
if rst = '1' then if rst = '1' then
smi_reg <= (others => '0'); smi_reg <= (others => '0');
smi_dat <= (others => '0'); smi_dat <= (others => '0');
smi_strb <= '0'; smi_strb <= '0';
rst_rxtx <= '1'; rst_rxtx <= '1';
initstate <= SMI_POR; initstate <= SMI_POR;
sendstate <= IDLE; sendstate <= IDLE;
delaycounter <= (others => '0'); delaycounter <= (others => '0');
elsif rising_edge(clk) then elsif rising_edge(clk) then
smi_strb <= '0'; smi_strb <= '0';
rst_rxtx <= '1'; rst_rxtx <= '1';
case initstate is case initstate is
when SMI_POR => when SMI_POR =>
delaycounter <= (others => '0'); delaycounter <= (others => '0');
initstate <= SMI_PORDELAY; initstate <= SMI_PORDELAY;
when SMI_PORDELAY => when SMI_PORDELAY =>
delaycounter <= delaycounter + 1; delaycounter <= delaycounter + 1;
if delaycounter = STARTUPDELAY then if delaycounter = STARTUPDELAY then
initstate <= RESET; initstate <= RESET;
end if; end if;
when RESET => when RESET =>
delaycounter <= (others => '0'); delaycounter <= (others => '0');
sendsmi((others => '0'), x"8000", DELAY); sendsmi((others => '0'), x"8000", DELAY);
when DELAY => when DELAY =>
delaycounter <= delaycounter + 1; delaycounter <= delaycounter + 1;
@ -227,8 +230,8 @@ begin -- architecture RTL
when INIT_COMPLETE => when INIT_COMPLETE =>
initstate <= INIT_COMPLETE; initstate <= INIT_COMPLETE;
if smi_busy = '0' then if smi_busy = '0' then
rst_rxtx <= '0'; rst_rxtx <= '0';
end if; end if;
end case; end case;
end if; end if;
end process initphy; end process initphy;
@ -246,6 +249,7 @@ begin -- architecture RTL
led1 <= '1'; led1 <= '1';
led2 <= '1'; led2 <= '1';
recv_cnt <= 0; recv_cnt <= 0;
pkg_type <= (others => '0');
mac <= (others => '0'); mac <= (others => '0');
elsif rising_edge(clk) then -- rising clock edge elsif rising_edge(clk) then -- rising clock edge
fifo_rst <= '0'; fifo_rst <= '0';
@ -254,6 +258,7 @@ begin -- architecture RTL
when PRE => when PRE =>
if sof = '1' then if sof = '1' then
recv_cnt <= 0; recv_cnt <= 0;
pkg_type <= (others => '0');
mac <= (others => '0'); mac <= (others => '0');
recv_state <= DESTMAC; recv_state <= DESTMAC;
led1 <= '1'; led1 <= '1';
@ -266,28 +271,35 @@ begin -- architecture RTL
elsif eth_strb = '1' then elsif eth_strb = '1' then
recv_cnt <= recv_cnt + 1; recv_cnt <= recv_cnt + 1;
mac <= mac(39 downto 0) & eth_dat; mac <= mac(39 downto 0) & eth_dat;
if recv_cnt = 5 then if recv_cnt = 5 and (mac(39 downto 0) & eth_dat) = DEFMAC then
recv_cnt <= 0; recv_cnt <= 0;
recv_state <= HEADER; recv_state <= SRCMAC;
end if; end if;
end if; end if;
when HEADER => when SRCMAC =>
led1 <= '0';
if eof = '1' then if eof = '1' then
recv_state <= PRE; recv_state <= PRE;
elsif eth_strb = '1' then elsif eth_strb = '1' then
recv_cnt <= recv_cnt + 1; recv_cnt <= recv_cnt + 1;
if recv_cnt = 7 then if recv_cnt 5 then -- SRC_MAC received
if mac = DEFMAC then recv_state <= TYPEFIELD
recv_state <= RECV; recv_cnt <= 0;
dat_cnt_s <= (others => '0');
else
recv_state <= PRE;
end if;
end if; end if;
end if; end if;
when TYPEFIELD =>
if eof = '1' then
recv_state <= PRE;
elsif eth_strb = '1' then
recv_cnt <= recv_cnt + 1;
pkg_type <= pkg_type(7 downto 0) & eth_dat;
if recv_cnt = 1 then -- Type received
recv_cnt <= 0;
recv_state <= RECV;
end if;
end if;
when RECV => when RECV =>
led2 <= '0'; led2 <= '0';
if eth_strb = '1' and fifo_full /= '1' then if eth_strb = '1' and fifo_full /= '1' then
@ -296,12 +308,19 @@ begin -- architecture RTL
dat_cnt_s <= dat_cnt_s +1; dat_cnt_s <= dat_cnt_s +1;
end if; end if;
if eof = '1' then if eof = '1' then
if crc_valid = '1' then -- or crc_valid = '0' then if crc_valid = '1' then
recv_state <= WAITFORACK; if pkg_type = PIPE_PKG then
fifo_data_avail <= '1'; -- Wait for further frames
--led2 <= '0'; -- This is also called with any
else -- undefined TYPEFIELD
--led2 <= '1'; recv_state <= PRE;
elsif pkg_type = FIN_PKG then
fifo_data_avail <= '1';
recv_state <= WAITFORACK;
else
recv_state <= PRE;
end if;
else -- Eth Frame invalid. Discard
fifo_rst <= '1'; fifo_rst <= '1';
recv_state <= PRE; recv_state <= PRE;
end if; end if;