library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity lattice_top is
	
	port (
		clk    : in    std_logic;
		rst    : in    std_logic;
		mdio   : inout std_logic;
		mdc    : out   std_logic;
		dv     : in    std_logic;
		rx     : in    std_logic_vector(1 downto 0);
		ws_out : out   std_logic);

end entity lattice_top;


architecture RTL of lattice_top is
signal rst_hw : std_logic;
begin  -- architecture RTL

rst_hw <= not rst;
	
top_1: entity work.top
	port map (
		clk	=> clk,
		rst_hw	=> rst_hw,
		mdio	=> mdio,
		mdc	=> mdc,
		rx	=> rx,
		dv	=> dv,
		led1	=> open,
		led2	=> open,
		dat_cnt => open,
		ws_out	=> ws_out);
	

end architecture RTL;