126 lines
5.2 KiB
VHDL
126 lines
5.2 KiB
VHDL
-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.10.0.111.2
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-- Module Version: 5.8
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--/usr/local/diamond/3.10_x64/ispfpga/bin/lin64/scuba -w -n fifo_dc -lang vhdl -synth synplify -bus_exp 7 -bb -arch xo2c00 -type ebfifo -depth 256 -width 8 -rwidth 8 -no_enable -pe 10 -pf 250
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-- Thu Apr 5 20:50:27 2018
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library IEEE;
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use IEEE.std_logic_1164.all;
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-- synopsys translate_off
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library MACHXO2;
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use MACHXO2.components.all;
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-- synopsys translate_on
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entity fifo_dc is
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port (
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Data: in std_logic_vector(7 downto 0);
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WrClock: in std_logic;
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RdClock: in std_logic;
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WrEn: in std_logic;
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RdEn: in std_logic;
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Reset: in std_logic;
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RPReset: in std_logic;
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Q: out std_logic_vector(7 downto 0);
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Empty: out std_logic;
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Full: out std_logic;
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AlmostEmpty: out std_logic;
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AlmostFull: out std_logic);
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end fifo_dc;
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architecture Structure of fifo_dc is
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-- internal signal declarations
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signal scuba_vhi: std_logic;
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signal Empty_int: std_logic;
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signal Full_int: std_logic;
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signal scuba_vlo: std_logic;
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-- local component declarations
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component VHI
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port (Z: out std_logic);
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end component;
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component VLO
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port (Z: out std_logic);
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end component;
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component FIFO8KB
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generic (FULLPOINTER1 : in String; FULLPOINTER : in String;
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AFPOINTER1 : in String; AFPOINTER : in String;
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AEPOINTER1 : in String; AEPOINTER : in String;
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ASYNC_RESET_RELEASE : in String; RESETMODE : in String;
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GSR : in String; CSDECODE_R : in String;
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CSDECODE_W : in String; REGMODE : in String;
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DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
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port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
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DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
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DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
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DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
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DI12: in std_logic; DI13: in std_logic;
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DI14: in std_logic; DI15: in std_logic;
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DI16: in std_logic; DI17: in std_logic;
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CSW0: in std_logic; CSW1: in std_logic;
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CSR0: in std_logic; CSR1: in std_logic;
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FULLI: in std_logic; EMPTYI: in std_logic;
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WE: in std_logic; RE: in std_logic; ORE: in std_logic;
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CLKW: in std_logic; CLKR: in std_logic; RST: in std_logic;
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RPRST: in std_logic; DO0: out std_logic;
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DO1: out std_logic; DO2: out std_logic;
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DO3: out std_logic; DO4: out std_logic;
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DO5: out std_logic; DO6: out std_logic;
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DO7: out std_logic; DO8: out std_logic;
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DO9: out std_logic; DO10: out std_logic;
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DO11: out std_logic; DO12: out std_logic;
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DO13: out std_logic; DO14: out std_logic;
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DO15: out std_logic; DO16: out std_logic;
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DO17: out std_logic; EF: out std_logic;
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AEF: out std_logic; AFF: out std_logic; FF: out std_logic);
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end component;
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attribute syn_keep : boolean;
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attribute NGD_DRC_MASK : integer;
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attribute NGD_DRC_MASK of Structure : architecture is 1;
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begin
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-- component instantiation statements
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scuba_vhi_inst: VHI
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port map (Z=>scuba_vhi);
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scuba_vlo_inst: VLO
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port map (Z=>scuba_vlo);
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fifo_dc_0_0: FIFO8KB
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generic map (FULLPOINTER1=> "0b00111111110000", FULLPOINTER=> "0b01000000000000",
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AFPOINTER1=> "0b00111110010000", AFPOINTER=> "0b00111110100000",
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AEPOINTER1=> "0b00000010110000", AEPOINTER=> "0b00000010100000",
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ASYNC_RESET_RELEASE=> "SYNC", GSR=> "DISABLED", RESETMODE=> "ASYNC",
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REGMODE=> "NOREG", CSDECODE_R=> "0b11", CSDECODE_W=> "0b11",
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DATA_WIDTH_R=> 18, DATA_WIDTH_W=> 18)
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port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
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DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
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DI8=>scuba_vlo, DI9=>scuba_vlo, DI10=>scuba_vlo,
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DI11=>scuba_vlo, DI12=>scuba_vlo, DI13=>scuba_vlo,
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DI14=>scuba_vlo, DI15=>scuba_vlo, DI16=>scuba_vlo,
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DI17=>scuba_vlo, CSW0=>scuba_vhi, CSW1=>scuba_vhi,
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CSR0=>scuba_vhi, CSR1=>scuba_vhi, FULLI=>Full_int,
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EMPTYI=>Empty_int, WE=>WrEn, RE=>RdEn, ORE=>RdEn,
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CLKW=>WrClock, CLKR=>RdClock, RST=>Reset, RPRST=>RPReset,
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DO0=>open, DO1=>open, DO2=>open, DO3=>open, DO4=>open,
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DO5=>open, DO6=>open, DO7=>open, DO8=>open, DO9=>Q(0),
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DO10=>Q(1), DO11=>Q(2), DO12=>Q(3), DO13=>Q(4), DO14=>Q(5),
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DO15=>Q(6), DO16=>Q(7), DO17=>open, EF=>Empty_int,
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AEF=>AlmostEmpty, AFF=>AlmostFull, FF=>Full_int);
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Empty <= Empty_int;
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Full <= Full_int;
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end Structure;
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-- synopsys translate_off
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library MACHXO2;
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configuration Structure_CON of fifo_dc is
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for Structure
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for all:VHI use entity MACHXO2.VHI(V); end for;
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for all:VLO use entity MACHXO2.VLO(V); end for;
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for all:FIFO8KB use entity MACHXO2.FIFO8KB(V); end for;
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end for;
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end Structure_CON;
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-- synopsys translate_on
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