40 lines
680 B
VHDL
40 lines
680 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity lattice_top is
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port (
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clk : in std_logic;
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rst : in std_logic;
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mdio : inout std_logic;
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mdc : out std_logic;
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dv : in std_logic;
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rx : in std_logic_vector(1 downto 0);
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ws_out : out std_logic);
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end entity lattice_top;
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architecture RTL of lattice_top is
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signal rst_hw : std_logic;
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begin -- architecture RTL
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rst_hw <= not rst;
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top_1: entity work.top
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port map (
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clk => clk,
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rst_hw => rst_hw,
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mdio => mdio,
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mdc => mdc,
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rx => rx,
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dv => dv,
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led1 => open,
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led2 => open,
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dat_cnt => open,
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ws_out => ws_out);
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end architecture RTL;
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