From 3c89949cb727c4bc6b500506110b41ffe9ebbe87 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Mario=20H=C3=BCttel?= <mario.huettel@gmx.net>
Date: Sun, 15 Apr 2018 21:20:30 +0200
Subject: [PATCH] fix SPI-Slave

---
 spi_slave.vhd | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/spi_slave.vhd b/spi_slave.vhd
index 81b1e11..4394622 100644
--- a/spi_slave.vhd
+++ b/spi_slave.vhd
@@ -85,14 +85,13 @@ begin  -- architecture RTL
 			shift_reg <= (others => '0');
 			dat_i_ack <= '0';
 			dat_o	  <= (others => '0');
-			miso_int  <= '0';
 			cnt	  <= 0;
 		elsif rising_edge(clk) then  -- rising clock edge
 			dat_i_ack  <= '0';
 			dat_o_strb <= '0';
 			if pos_edge = '1' and cs_sync = '0' then
 				shift_reg <= shift_reg(DAT_WIDTH-2 downto 0) & mosi_sync;
-				miso_int  <= shift_reg(7);
+				
 				if cnt < DAT_WIDTH-1 then
 					cnt <= cnt + 1;
 				else
@@ -107,7 +106,7 @@ begin  -- architecture RTL
 			end if;
 		end if;
 	end process shifter;
-
+	miso_int  <= shift_reg(7);
 	miso <= miso_int when cs = '0' else 'Z';
 
 end architecture RTL;