library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity bench is

end entity bench;

architecture sim of bench is
	signal clk    : std_logic;
	signal rst_hw : std_logic;
	signal sck    : std_logic;
	signal mosi   : std_logic;
	signal cs     : std_logic;
	signal ready  : std_logic;
	signal ws_out : std_logic;
begin  -- architecture sim

	top_1 : entity work.top
		port map (
			clk    => clk,
			rst_hw => rst_hw,
			sck    => sck,
			mosi   => mosi,
			cs     => cs,
			ready  => ready,
			ws_out => ws_out);

	clk_gen : process is
	begin
		clk <= '0';
		wait for 10 ns;
		clk <= '1';
		wait for 10 ns;
	end process clk_gen;

	rst_gen : process is
	begin
		rst_hw <= '1';
		wait for 15 ns;
		rst_hw <= '0';
		wait;
	end process rst_gen;

	sck_gen : process is
	begin
		sck <= '0';
		wait for 40 ns;
		sck <= '1';
		wait for 40 ns;
	end process sck_gen;

	send_spi : process is
		procedure send24(dat : in std_logic_vector(23 downto 0)) is
			variable data : std_logic_vector(dat'range);
		begin
			cs   <= '1';
			if ready /= '1' then
				wait until ready = '1';
			end if;			
			wait for 30 ns;
			data := dat;
			wait until falling_edge(sck);
			cs   <= '0';
			mosi <= data(23);
			data := data(22 downto 0) & '0';
			wait until falling_edge(sck);
			cs   <= '0';
			mosi <= data(23);
			data := data(22 downto 0) & '0';
			wait until falling_edge(sck);
			cs   <= '0';
			mosi <= data(23);
			data := data(22 downto 0) & '0';
			wait until falling_edge(sck);
			cs   <= '0';
			mosi <= data(23);
			data := data(22 downto 0) & '0';
			wait until falling_edge(sck);
			cs   <= '0';
			mosi <= data(23);
			data := data(22 downto 0) & '0';
			wait until falling_edge(sck);
			cs   <= '0';
			mosi <= data(23);
			data := data(22 downto 0) & '0';
			wait until falling_edge(sck);
			cs   <= '0';
			mosi <= data(23);
			data := data(22 downto 0) & '0';
			wait until falling_edge(sck);
			cs   <= '0';
			mosi <= data(23);
			data := data(22 downto 0) & '0';
			wait until falling_edge(sck);
			cs   <= '0';
			mosi <= data(23);
			data := data(22 downto 0) & '0';
			wait until falling_edge(sck);
			cs   <= '0';
			mosi <= data(23);
			data := data(22 downto 0) & '0';
			wait until falling_edge(sck);
			cs   <= '0';
			mosi <= data(23);
			data := data(22 downto 0) & '0';
			wait until falling_edge(sck);
			cs   <= '0';
			mosi <= data(23);
			data := data(22 downto 0) & '0';
			wait until falling_edge(sck);
			cs   <= '0';
			mosi <= data(23);
			data := data(22 downto 0) & '0';
			wait until falling_edge(sck);
			cs   <= '0';
			mosi <= data(23);
			data := data(22 downto 0) & '0';
			wait until falling_edge(sck);
			cs   <= '0';
			mosi <= data(23);
			data := data(22 downto 0) & '0';
			wait until falling_edge(sck);
			cs   <= '0';
			mosi <= data(23);
			data := data(22 downto 0) & '0';
			wait until falling_edge(sck);
			cs   <= '0';
			mosi <= data(23);
			data := data(22 downto 0) & '0';
			wait until falling_edge(sck);
			cs   <= '0';
			mosi <= data(23);
			data := data(22 downto 0) & '0';
			wait until falling_edge(sck);
			cs   <= '0';
			mosi <= data(23);
			data := data(22 downto 0) & '0';
			wait until falling_edge(sck);
			cs   <= '0';
			mosi <= data(23);
			data := data(22 downto 0) & '0';
			wait until falling_edge(sck);
			cs   <= '0';
			mosi <= data(23);
			data := data(22 downto 0) & '0';
			wait until falling_edge(sck);
			cs   <= '0';
			mosi <= data(23);
			data := data(22 downto 0) & '0';
			wait until falling_edge(sck);
			cs   <= '0';
			mosi <= data(23);
			data := data(22 downto 0) & '0';
			wait until falling_edge(sck);
			cs   <= '0';
			mosi <= data(23);
			data := data(22 downto 0) & '0';
			wait until falling_edge(sck);
			cs   <= '1';
		end send24;
	begin
		cs <= '1';
		wait for 50 ns;
		send24(x"FF0055");
send24(x"CCFFAA");
		send24(x"FF0055");
send24(x"CCFFAA");
		send24(x"FF0055");
send24(x"CCFFAA");
		send24(x"FF0055");
send24(x"CCFFAA");
		send24(x"FF0055");
send24(x"CCFFAA");
		send24(x"FF0055");
send24(x"CCFFAA");
		send24(x"FF0055");
send24(x"CCFFAA");
		send24(x"FF0055");
send24(x"CCFFAA");
		send24(x"FF0055");
send24(x"CCFFAA");
		send24(x"FF0055");
send24(x"CCFFAA");
		wait;
	end process send_spi;
end architecture sim;