From abdabd8eb7a43dfbc2ec12d939e5fa7ba3720842 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Mario=20H=C3=BCttel?= <mario.huettel@gmx.net>
Date: Thu, 17 Oct 2019 20:16:14 +0200
Subject: [PATCH] Fix definition in STM header file and add header files for
 drivers

---
 include/delay.h       | 13 +++++++++++++
 include/lcd.h         | 43 +++++++++++++++++++++++++++++++++++++++++++
 include/stm32f030x6.h | 11 +++++++++--
 3 files changed, 65 insertions(+), 2 deletions(-)
 create mode 100644 include/delay.h
 create mode 100644 include/lcd.h

diff --git a/include/delay.h b/include/delay.h
new file mode 100644
index 0000000..9bc1614
--- /dev/null
+++ b/include/delay.h
@@ -0,0 +1,13 @@
+#ifndef __DELAY_H__
+#define __DELAY_H__
+
+#include <stdint.h>
+
+extern volatile uint32_t tick;
+
+/**
+ * @brief wait for specific time in ms. May not be caleed from interrupt context
+ */
+void delay_ms(uint32_t ms);
+
+#endif /* __DELAY_H__ */
diff --git a/include/lcd.h b/include/lcd.h
new file mode 100644
index 0000000..2935ae3
--- /dev/null
+++ b/include/lcd.h
@@ -0,0 +1,43 @@
+#ifndef __LCD_H__
+#define __LCD_H__
+
+#include <stm32f0xx.h>
+
+#define LCD_DPORT		(GPIOA)
+#define LCD_DATA_BIT_OFFSET	(0)
+#define LCD_RS			(9)
+#define LCD_E			(10)
+
+#define LCD_DATA_MASK		(0xFU << LCD_DATA_BIT_OFFSET)
+#define	LCD_RS_MASK		(1U << LCD_RS)
+#define	LCD_E_MASK		(1U << LCD_E)
+
+/**
+ * @brief Initialize 4 bit LCD mode. GPIOs have to be set up prior to any call of this function
+ */
+void lcd_init(void);
+
+/**
+ * @brief Clear display
+ */
+void lcd_clear(void);
+
+/**
+ * @brief Set cursor position to 0/0
+ */
+void lcd_home(void);
+
+/**
+ * @brief Set cursor to position \p x \p y
+ * @param x Position in line
+ * @param y Line
+ */
+void lcd_setcursor(uint8_t x, uint8_t y);
+
+/**
+ * @brief Write string to current cursor position
+ * @param String to write
+ */
+void lcd_string(const char *data);
+
+#endif /* __LCD_H__ */
diff --git a/include/stm32f030x6.h b/include/stm32f030x6.h
index c06fe71..b1c6ae9 100644
--- a/include/stm32f030x6.h
+++ b/include/stm32f030x6.h
@@ -365,8 +365,15 @@ typedef struct
 {
   __IO uint32_t CR1;      /*!< SPI Control register 1 (not used in I2S mode),       Address offset: 0x00 */
   __IO uint32_t CR2;      /*!< SPI Control register 2,                              Address offset: 0x04 */
-  __IO uint32_t SR;       /*!< SPI Status register,                                 Address offset: 0x08 */
-  __IO uint32_t DR;       /*!< SPI data register,                                   Address offset: 0x0C */
+  __IO uint32_t SR;		/*!< SPI Status register,                                 Address offset: 0x08 */
+  union DR_ {
+  __IO uint16_t DR16;       /*!< SPI data register,                                   Address offset: 0x0C */
+  struct DR8_ {
+	__IO uint8_t DR8_1;
+	__IO uint8_t DR8_2;
+  } DR8;
+  } DR;
+  __IO uint16_t DR_DUMMY;
   __IO uint32_t CRCPR;    /*!< SPI CRC polynomial register (not used in I2S mode),  Address offset: 0x10 */
   __IO uint32_t RXCRCR;   /*!< SPI Rx CRC register (not used in I2S mode),          Address offset: 0x14 */
   __IO uint32_t TXCRCR;   /*!< SPI Tx CRC register (not used in I2S mode),          Address offset: 0x18 */