741 lines
35 KiB
C
741 lines
35 KiB
C
/**************************************************************************//**
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* @file core_cm0.h
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* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
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* @version V4.10
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* @date 18. March 2015
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*
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* @note
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*
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******************************************************************************/
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/* Copyright (c) 2009 - 2015 ARM LIMITED
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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- Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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- Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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- Neither the name of ARM nor the names of its contributors may be used
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to endorse or promote products derived from this software without
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specific prior written permission.
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*
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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---------------------------------------------------------------------------*/
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#if defined ( __ICCARM__ )
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#pragma system_include /* treat file as system include file for MISRA check */
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#endif
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#ifndef __CORE_CM0_H_GENERIC
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#define __CORE_CM0_H_GENERIC
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
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CMSIS violates the following MISRA-C:2004 rules:
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\li Required Rule 8.5, object/function definition in header file.<br>
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Function definitions in header files are used to allow 'inlining'.
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\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
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Unions are used for effective representation of core registers.
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\li Advisory Rule 19.7, Function-like macro defined.<br>
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Function-like macros are used to allow more efficient code.
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*/
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/*******************************************************************************
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* CMSIS definitions
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******************************************************************************/
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/** \ingroup Cortex_M0
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@{
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*/
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/* CMSIS CM0 definitions */
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#define __CM0_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
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#define __CM0_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
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#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
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__CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
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#define __CORTEX_M (0x00) /*!< Cortex-M Core */
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#if defined ( __CC_ARM )
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#define __ASM __asm /*!< asm keyword for ARM Compiler */
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#define __INLINE __inline /*!< inline keyword for ARM Compiler */
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#define __STATIC_INLINE static __inline
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#elif defined ( __GNUC__ )
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#define __ASM __asm /*!< asm keyword for GNU Compiler */
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#define __INLINE inline /*!< inline keyword for GNU Compiler */
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#define __STATIC_INLINE static inline
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#elif defined ( __ICCARM__ )
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#define __ASM __asm /*!< asm keyword for IAR Compiler */
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#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
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#define __STATIC_INLINE static inline
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#elif defined ( __TMS470__ )
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#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
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#define __STATIC_INLINE static inline
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#elif defined ( __TASKING__ )
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#define __ASM __asm /*!< asm keyword for TASKING Compiler */
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#define __INLINE inline /*!< inline keyword for TASKING Compiler */
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#define __STATIC_INLINE static inline
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#elif defined ( __CSMC__ )
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#define __packed
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#define __ASM _asm /*!< asm keyword for COSMIC Compiler */
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#define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
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#define __STATIC_INLINE static inline
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#endif
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/** __FPU_USED indicates whether an FPU is used or not.
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This core does not support an FPU at all
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*/
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#define __FPU_USED 0
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#if defined ( __CC_ARM )
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#if defined __TARGET_FPU_VFP
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#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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#endif
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#elif defined ( __GNUC__ )
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#if defined (__VFP_FP__) && !defined(__SOFTFP__)
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#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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#endif
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#elif defined ( __ICCARM__ )
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#if defined __ARMVFP__
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#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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#endif
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#elif defined ( __TMS470__ )
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#if defined __TI__VFP_SUPPORT____
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#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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#endif
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#elif defined ( __TASKING__ )
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#if defined __FPU_VFP__
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#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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#endif
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#elif defined ( __CSMC__ ) /* Cosmic */
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#if ( __CSMC__ & 0x400) // FPU present for parser
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#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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#endif
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#endif
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#include <stdint.h> /* standard types definitions */
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#include <core_cmInstr.h> /* Core Instruction Access */
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#include <core_cmFunc.h> /* Core Function Access */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __CORE_CM0_H_GENERIC */
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#ifndef __CMSIS_GENERIC
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#ifndef __CORE_CM0_H_DEPENDANT
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#define __CORE_CM0_H_DEPENDANT
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* check device defines and use defaults */
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#if defined __CHECK_DEVICE_DEFINES
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#ifndef __CM0_REV
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#define __CM0_REV 0x0000
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#warning "__CM0_REV not defined in device header file; using default!"
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#endif
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#ifndef __NVIC_PRIO_BITS
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#define __NVIC_PRIO_BITS 2
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#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
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#endif
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#ifndef __Vendor_SysTickConfig
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#define __Vendor_SysTickConfig 0
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#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
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#endif
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#endif
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/* IO definitions (access restrictions to peripheral registers) */
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/**
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\defgroup CMSIS_glob_defs CMSIS Global Defines
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<strong>IO Type Qualifiers</strong> are used
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\li to specify the access to peripheral variables.
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\li for automatic generation of peripheral register debug information.
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*/
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#ifdef __cplusplus
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#define __I volatile /*!< Defines 'read only' permissions */
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#else
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#define __I volatile const /*!< Defines 'read only' permissions */
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#endif
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#define __O volatile /*!< Defines 'write only' permissions */
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#define __IO volatile /*!< Defines 'read / write' permissions */
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/*@} end of group Cortex_M0 */
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/*******************************************************************************
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* Register Abstraction
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Core Register contain:
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- Core Register
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- Core NVIC Register
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- Core SCB Register
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- Core SysTick Register
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******************************************************************************/
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/** \defgroup CMSIS_core_register Defines and Type Definitions
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\brief Type definitions and defines for Cortex-M processor based devices.
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*/
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/** \ingroup CMSIS_core_register
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\defgroup CMSIS_CORE Status and Control Registers
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\brief Core Register type definitions.
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@{
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*/
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/** \brief Union type to access the Application Program Status Register (APSR).
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*/
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typedef union
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{
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struct
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{
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uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
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uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
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uint32_t C:1; /*!< bit: 29 Carry condition code flag */
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uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
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uint32_t N:1; /*!< bit: 31 Negative condition code flag */
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} b; /*!< Structure used for bit access */
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uint32_t w; /*!< Type used for word access */
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} APSR_Type;
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/* APSR Register Definitions */
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#define APSR_N_Pos 31 /*!< APSR: N Position */
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#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
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#define APSR_Z_Pos 30 /*!< APSR: Z Position */
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#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
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#define APSR_C_Pos 29 /*!< APSR: C Position */
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#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
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#define APSR_V_Pos 28 /*!< APSR: V Position */
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#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
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/** \brief Union type to access the Interrupt Program Status Register (IPSR).
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*/
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typedef union
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{
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struct
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{
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uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
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uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
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} b; /*!< Structure used for bit access */
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uint32_t w; /*!< Type used for word access */
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} IPSR_Type;
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/* IPSR Register Definitions */
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#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
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#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
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/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
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*/
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typedef union
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{
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struct
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{
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uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
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uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
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uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
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uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
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uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
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uint32_t C:1; /*!< bit: 29 Carry condition code flag */
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uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
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uint32_t N:1; /*!< bit: 31 Negative condition code flag */
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} b; /*!< Structure used for bit access */
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uint32_t w; /*!< Type used for word access */
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} xPSR_Type;
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/* xPSR Register Definitions */
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#define xPSR_N_Pos 31 /*!< xPSR: N Position */
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#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
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#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
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#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
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#define xPSR_C_Pos 29 /*!< xPSR: C Position */
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#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
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#define xPSR_V_Pos 28 /*!< xPSR: V Position */
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#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
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#define xPSR_T_Pos 24 /*!< xPSR: T Position */
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#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
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#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
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#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
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/** \brief Union type to access the Control Registers (CONTROL).
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*/
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typedef union
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{
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struct
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{
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uint32_t _reserved0:1; /*!< bit: 0 Reserved */
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uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
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uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
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} b; /*!< Structure used for bit access */
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uint32_t w; /*!< Type used for word access */
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} CONTROL_Type;
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/* CONTROL Register Definitions */
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#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
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#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
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/*@} end of group CMSIS_CORE */
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/** \ingroup CMSIS_core_register
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\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
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\brief Type definitions for the NVIC Registers
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@{
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*/
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/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
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*/
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typedef struct
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{
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__IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
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uint32_t RESERVED0[31];
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__IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
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uint32_t RSERVED1[31];
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__IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
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uint32_t RESERVED2[31];
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__IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
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uint32_t RESERVED3[31];
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uint32_t RESERVED4[64];
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__IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
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} NVIC_Type;
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/*@} end of group CMSIS_NVIC */
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/** \ingroup CMSIS_core_register
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\defgroup CMSIS_SCB System Control Block (SCB)
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\brief Type definitions for the System Control Block Registers
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@{
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*/
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/** \brief Structure type to access the System Control Block (SCB).
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*/
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typedef struct
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{
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__I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
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__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
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uint32_t RESERVED0;
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__IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
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__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
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__IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
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uint32_t RESERVED1;
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__IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
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__IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
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} SCB_Type;
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/* SCB CPUID Register Definitions */
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#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
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#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
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#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
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#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
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#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
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#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
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#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
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#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
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#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
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#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
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/* SCB Interrupt Control State Register Definitions */
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#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
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#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
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#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
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#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
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#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
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#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
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#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
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#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
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#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
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#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
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#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
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#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
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#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
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#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
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#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
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#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
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#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
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#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
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/* SCB Application Interrupt and Reset Control Register Definitions */
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#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
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#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
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#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
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#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
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#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
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#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
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#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
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#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
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#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
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#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
|
|
|
|
/* SCB System Control Register Definitions */
|
|
#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
|
|
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
|
|
|
|
#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
|
|
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
|
|
|
|
#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
|
|
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
|
|
|
|
/* SCB Configuration Control Register Definitions */
|
|
#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
|
|
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
|
|
|
|
#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
|
|
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
|
|
|
|
/* SCB System Handler Control and State Register Definitions */
|
|
#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
|
|
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
|
|
|
|
/*@} end of group CMSIS_SCB */
|
|
|
|
|
|
/** \ingroup CMSIS_core_register
|
|
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
|
|
\brief Type definitions for the System Timer Registers.
|
|
@{
|
|
*/
|
|
|
|
/** \brief Structure type to access the System Timer (SysTick).
|
|
*/
|
|
typedef struct
|
|
{
|
|
__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
|
|
__IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
|
|
__IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
|
|
__I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
|
|
} SysTick_Type;
|
|
|
|
/* SysTick Control / Status Register Definitions */
|
|
#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
|
|
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
|
|
|
|
#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
|
|
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
|
|
|
|
#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
|
|
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
|
|
|
|
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
|
|
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
|
|
|
|
/* SysTick Reload Register Definitions */
|
|
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
|
|
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
|
|
|
|
/* SysTick Current Register Definitions */
|
|
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
|
|
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
|
|
|
|
/* SysTick Calibration Register Definitions */
|
|
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
|
|
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
|
|
|
|
#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
|
|
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
|
|
|
|
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
|
|
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
|
|
|
|
/*@} end of group CMSIS_SysTick */
|
|
|
|
|
|
/** \ingroup CMSIS_core_register
|
|
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
|
|
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
|
|
are only accessible over DAP and not via processor. Therefore
|
|
they are not covered by the Cortex-M0 header file.
|
|
@{
|
|
*/
|
|
/*@} end of group CMSIS_CoreDebug */
|
|
|
|
|
|
/** \ingroup CMSIS_core_register
|
|
\defgroup CMSIS_core_base Core Definitions
|
|
\brief Definitions for base addresses, unions, and structures.
|
|
@{
|
|
*/
|
|
|
|
/* Memory mapping of Cortex-M0 Hardware */
|
|
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
|
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
|
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
|
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
|
|
|
|
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
|
|
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
|
|
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
|
|
|
|
|
/*@} */
|
|
|
|
|
|
|
|
/*******************************************************************************
|
|
* Hardware Abstraction Layer
|
|
Core Function Interface contains:
|
|
- Core NVIC Functions
|
|
- Core SysTick Functions
|
|
- Core Register Access Functions
|
|
******************************************************************************/
|
|
/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
|
|
*/
|
|
|
|
|
|
|
|
/* ########################## NVIC functions #################################### */
|
|
/** \ingroup CMSIS_Core_FunctionInterface
|
|
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
|
|
\brief Functions that manage interrupts and exceptions via the NVIC.
|
|
@{
|
|
*/
|
|
|
|
/* Interrupt Priorities are WORD accessible only under ARMv6M */
|
|
/* The following MACROS handle generation of the register offset and byte masks */
|
|
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
|
|
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
|
|
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
|
|
|
|
|
|
/** \brief Enable External Interrupt
|
|
|
|
The function enables a device-specific interrupt in the NVIC interrupt controller.
|
|
|
|
\param [in] IRQn External interrupt number. Value cannot be negative.
|
|
*/
|
|
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
|
|
{
|
|
NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
|
}
|
|
|
|
|
|
/** \brief Disable External Interrupt
|
|
|
|
The function disables a device-specific interrupt in the NVIC interrupt controller.
|
|
|
|
\param [in] IRQn External interrupt number. Value cannot be negative.
|
|
*/
|
|
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
|
|
{
|
|
NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
|
}
|
|
|
|
|
|
/** \brief Get Pending Interrupt
|
|
|
|
The function reads the pending register in the NVIC and returns the pending bit
|
|
for the specified interrupt.
|
|
|
|
\param [in] IRQn Interrupt number.
|
|
|
|
\return 0 Interrupt status is not pending.
|
|
\return 1 Interrupt status is pending.
|
|
*/
|
|
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
|
{
|
|
return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
|
}
|
|
|
|
|
|
/** \brief Set Pending Interrupt
|
|
|
|
The function sets the pending bit of an external interrupt.
|
|
|
|
\param [in] IRQn Interrupt number. Value cannot be negative.
|
|
*/
|
|
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
|
{
|
|
NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
|
}
|
|
|
|
|
|
/** \brief Clear Pending Interrupt
|
|
|
|
The function clears the pending bit of an external interrupt.
|
|
|
|
\param [in] IRQn External interrupt number. Value cannot be negative.
|
|
*/
|
|
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
|
{
|
|
NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
|
}
|
|
|
|
|
|
/** \brief Set Interrupt Priority
|
|
|
|
The function sets the priority of an interrupt.
|
|
|
|
\note The priority cannot be set for every core interrupt.
|
|
|
|
\param [in] IRQn Interrupt number.
|
|
\param [in] priority Priority to set.
|
|
*/
|
|
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
|
{
|
|
if((int32_t)(IRQn) < 0) {
|
|
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
|
(((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
|
}
|
|
else {
|
|
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
|
(((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
|
}
|
|
}
|
|
|
|
|
|
/** \brief Get Interrupt Priority
|
|
|
|
The function reads the priority of an interrupt. The interrupt
|
|
number can be positive to specify an external (device specific)
|
|
interrupt, or negative to specify an internal (core) interrupt.
|
|
|
|
|
|
\param [in] IRQn Interrupt number.
|
|
\return Interrupt Priority. Value is aligned automatically to the implemented
|
|
priority bits of the microcontroller.
|
|
*/
|
|
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
|
|
{
|
|
|
|
if((int32_t)(IRQn) < 0) {
|
|
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
|
|
}
|
|
else {
|
|
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
|
|
}
|
|
}
|
|
|
|
|
|
/** \brief System Reset
|
|
|
|
The function initiates a system reset request to reset the MCU.
|
|
*/
|
|
__STATIC_INLINE void NVIC_SystemReset(void)
|
|
{
|
|
__DSB(); /* Ensure all outstanding memory accesses included
|
|
buffered write are completed before reset */
|
|
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
|
SCB_AIRCR_SYSRESETREQ_Msk);
|
|
__DSB(); /* Ensure completion of memory access */
|
|
while(1) { __NOP(); } /* wait until reset */
|
|
}
|
|
|
|
/*@} end of CMSIS_Core_NVICFunctions */
|
|
|
|
|
|
|
|
/* ################################## SysTick function ############################################ */
|
|
/** \ingroup CMSIS_Core_FunctionInterface
|
|
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
|
|
\brief Functions that configure the System.
|
|
@{
|
|
*/
|
|
|
|
#if (__Vendor_SysTickConfig == 0)
|
|
|
|
/** \brief System Tick Configuration
|
|
|
|
The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
|
|
Counter is in free running mode to generate periodic interrupts.
|
|
|
|
\param [in] ticks Number of ticks between two interrupts.
|
|
|
|
\return 0 Function succeeded.
|
|
\return 1 Function failed.
|
|
|
|
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
|
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
|
must contain a vendor-specific implementation of this function.
|
|
|
|
*/
|
|
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
|
{
|
|
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
|
|
|
|
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
|
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
|
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
|
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
|
SysTick_CTRL_TICKINT_Msk |
|
|
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
|
return (0UL); /* Function successful */
|
|
}
|
|
|
|
#endif
|
|
|
|
/*@} end of CMSIS_Core_SysTickFunctions */
|
|
|
|
|
|
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* __CORE_CM0_H_DEPENDANT */
|
|
|
|
#endif /* __CMSIS_GENERIC */
|