From 702cb5f884e41dec957f381f1dc68bd56e7128f8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Mario=20H=C3=BCttel?= Date: Wed, 26 Apr 2017 14:19:45 +0200 Subject: [PATCH] Update page 'M_CAN Driver Usage Device Tree' --- M_CAN Driver Usage Device Tree.md | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/M_CAN Driver Usage Device Tree.md b/M_CAN Driver Usage Device Tree.md index 87e40c0..7c8b0cc 100644 --- a/M_CAN Driver Usage Device Tree.md +++ b/M_CAN Driver Usage Device Tree.md @@ -30,16 +30,22 @@ mcan0: can@0xff240000 { }; ``` + +----- + + ### 'reg' Values The M_CAN device node consists of two memory regions. The first is the register address space of the M_CAN. The M_CAN uses a 9 bit address space. Therefore it is 0x200 long. The second memory region is the _whole_ message RAM. this RAM can be shared betwen different M_CAN nodes. In this example it has a length of 0x4000 bytes. +----- ### Interrupts It is necessary to configure interrupt line 0 of the M_CAN according to your SoC. Although interrupt line 1 is specified in some device trees, it will not be used by the driver. +----- ### Clocks The M_CAN needs two clocks. The first clock *hclk* is used for the internal bus interface. Thesecond clock *cclk* is used for the CAN communication. It should be one of the following values: @@ -48,6 +54,7 @@ cclk = {20 MHz, 40 MHz, 80 MHz} It is important, due to internal clock crossings, that *hclk* is always higher than or equal to *cclk*. +----- ### MRAM Config The last device tree value configures the setup and layout of the MRAM (message RAM). @@ -61,7 +68,7 @@ The *offset* value defines the address offset in bytes inside the MRAM region. E The remaining values configure the amout of elments for different FIFOs and Buffers. -#### M_CAN version 3.0.x +#### For M_CAN Version 3.0.x For M_CAN versions 3.0.x, the driver only uses the RX FIFO 0 and *one*(!) TX Buffer. @@ -73,7 +80,7 @@ is a valid configuration with 32 RX FIFO elements. The other values cna be set t Also it is possible to configure more than one TX Buffer. However, only one will be used. -#### M_CAN version >=3.1.x +#### For M_CAN Version >=3.1.x For versions greater than 3.1.x, the driver uses the TX FIFO to improve performance. For correct operation it also needs th TX Event FIFO. Therefore the TX Event FIFO value has to be configured. To prevent overflows it is recommended to use at least as many TX Event FIFO elements as TX FIFO Elements.