#include #include static volatile bool dmx_new_data_avail = false; static uint32_t dmx_base_channel; static uint8_t dmx_channel_data[DMX_USED_CHANNEL_COUNT]; void dmx_init(uint32_t base_channel) { int i; uint8_t *ptr; dmx_new_data_avail = false; for (i = 0, ptr = dmx_channel_data; i < DMX_USED_CHANNEL_COUNT; i++, ptr++) { *ptr = 0u; } dmx_base_channel = base_channel; /* Enable GPIOA and USART1 clock */ RCC->AHBENR |= RCC_AHBENR_GPIOAEN; RCC->APB2ENR |= RCC_APB2ENR_USART1EN; /* Switch RXTX pin low, activating permanent READ mode */ GPIOA->MODER |= (0x1<<(2*5)); GPIOA->BRR |= (1<<5); /* Switch PA10 to RX alternate function of USART1 (AF1) */ GPIOA->MODER |= (0x2<<(2*10)); GPIOA->AFR[1] |=(0x1<<(4*2)); /* Set baudrate: 48MHz / 250k = 129 */ USART1->BRR = 192u; USART1->CR3 = USART_CR3_EIE; USART1->CR2 = USART_CR2_STOP_1; USART1->CR1 = USART_CR1_RXNEIE | USART_CR1_RE | USART_CR1_UE; NVIC_EnableIRQ(USART1_IRQn); } bool dmx_new_data_available() { return dmx_new_data_avail; } const uint8_t *dmx_get_data() { return dmx_channel_data; } void USART1_IRQHandler(void) { uint32_t isr; volatile uint8_t dreg; isr = USART1->ISR; USART1->ICR = USART_ICR_ORECF | USART_ICR_NCF | USART_ICR_FECF; if (isr & USART_ISR_RXNE) { dreg = (uint8_t)USART1->RDR; dmx_channel_data[0] = dreg; } __DSB(); }