127 lines
2.7 KiB
C
127 lines
2.7 KiB
C
#include <ring-light/dmx.h>
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#include <stm32f0xx.h>
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static uint32_t dmx_base_channel;
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enum dmx_rx_state_enum {
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DMX_RX_WAIT_FOR_BREAK = 0,
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DMX_RX_DATA,
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};
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static volatile bool break_received;
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/**
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* @brief DMX data received. Contains the whole DMX universe including the first 0 byte.
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* The controller does check the first byte to be zero.
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*/
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static volatile uint8_t dmx_channel_data[DMX_UNIVERSE_SIZE + 1];
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void dmx_init(uint32_t base_channel)
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{
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int i;
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volatile uint8_t *ptr;
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for (i = 0, ptr = dmx_channel_data; i < DMX_USED_CHANNEL_COUNT; i++, ptr++) {
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*ptr = 0u;
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}
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dmx_base_channel = base_channel;
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break_received = false;
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/* Enable GPIOA and USART1 clock */
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RCC->AHBENR |= RCC_AHBENR_GPIOAEN | RCC_AHBENR_DMAEN;
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RCC->APB2ENR |= RCC_APB2ENR_USART1EN;
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/* Switch RXTX pin low, activating permanent READ mode */
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GPIOA->MODER |= (0x1<<(2*5));
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GPIOA->BRR |= (1<<5);
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/* Switch PA10 to RX alternate function of USART1 (AF1) */
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GPIOA->MODER |= (0x2<<(2*10));
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GPIOA->AFR[1] |=(0x1<<(4*2));
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/* Set baudrate: 48MHz / 250k = 129 */
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USART1->BRR = 192u;
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USART1->CR3 = USART_CR3_EIE;
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USART1->CR2 = USART_CR2_STOP_1;
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USART1->CR1 = USART_CR1_RXNEIE | USART_CR1_RE | USART_CR1_UE;
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/* Map USART1 RX to DMA Channel 3 */
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SYSCFG->CFGR1 &= ~SYSCFG_CFGR1_USART1RX_DMA_RMP;
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DMA1_Channel3->CCR = DMA_CCR_PL_1 | DMA_CCR_MINC | DMA_CCR_TCIE;
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NVIC_EnableIRQ(DMA1_Channel2_3_IRQn);
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NVIC_EnableIRQ(USART1_IRQn);
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}
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const uint8_t *dmx_get_data()
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{
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return (const uint8_t *)dmx_channel_data;
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}
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void USART1_IRQHandler(void)
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{
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uint32_t isr;
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isr = USART1->ISR;
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USART1->ICR = USART_ICR_ORECF | USART_ICR_NCF | USART_ICR_FECF;
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if (isr & USART_ISR_FE) {
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/* Frame error received. Start of DMX frame */
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/* Flush RX data */
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USART1->RQR = USART_RQR_RXFRQ;
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USART1->CR3 |= USART_CR3_DMAR;
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DMA1_Channel3->CCR &= ~DMA_CCR_EN;
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DMA1_Channel3->CMAR = (uint32_t)dmx_channel_data;
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DMA1_Channel3->CPAR = (uint32_t)&USART1->RDR;
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DMA1_Channel3->CNDTR = DMX_UNIVERSE_SIZE + 1;
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DMA1_Channel3->CCR |= DMA_CCR_EN;
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USART1->CR3 |= USART_CR3_DMAR;
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break_received = true;
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} else if (isr & USART_ISR_RXNE) {
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}
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__DSB();
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}
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void DMA_CH2_3_DMA2_CH1_2_IRQHandler(void)
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{
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uint32_t isr;
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isr = DMA1->ISR;
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/* Only clear the interupts of channel 2 (bits 11:9) */
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DMA1->IFCR = isr & 0xF00;
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if (isr & DMA_ISR_TCIF3) {
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DMA1->ISR;
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}
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__DSB();
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}
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bool dmx_poll_break_received(void)
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{
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bool ret;
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/* Atomically reset the flag */
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__disable_irq();
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ret = break_received;
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break_received = false;
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__enable_irq();
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return ret;
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}
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bool dmx_enough_data_received()
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{
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uint32_t received_count = (DMX_UNIVERSE_SIZE + 1) - DMA1_Channel3->CNDTR;
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if (received_count > (dmx_base_channel + DMX_USED_CHANNEL_COUNT)) {
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return true;
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}
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return false;
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}
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