#ifndef __SHELL_UART_CONFIG_H__
#define __SHELL_UART_CONFIG_H__

#define SHELL_UART_RECEIVE_DMA_STREAM DMA2_Stream5

#define SHELL_UART_SEND_DMA_STREAM DMA2_Stream7

#define SHELL_UART_PERIPH USART1
#define SHELL_UART_RCC_REG RCC->APB2ENR
#define SHELL_UART_RCC_MASK RCC_APB2ENR_USART1EN

#define SHELL_UART_RX_DMA_TRIGGER 4U
#define SHELL_UART_TX_DMA_TRIGGER 4U

#ifdef DEBUGBUILD

#define SHELL_UART_PORT GPIOA
#define SHELL_UART_PORT_RCC_MASK RCC_AHB1ENR_GPIOAEN
#define SHELL_UART_RX_PIN 10
#define SHELL_UART_TX_PIN 9
#define SHELL_UART_RX_PIN_ALTFUNC 7
#define SHELL_UART_TX_PIN_ALTFUNC 7
#else

#endif

/* UART_DIV is 45.5625 => 115200 @ 84 MHz */
#define SHELL_UART_DIV_FRACTION 9U /* Equals 9/16 = 0.5625 */
#define SHELL_UART_DIV_MANTISSA 45U /* Equals 45 */

#define SHELL_UART_BRR_REG_VALUE ((SHELL_UART_DIV_MANTISSA<<4) | SHELL_UART_DIV_FRACTION);

#endif /* __SHELL_UART_CONFIG_H__ */
