2021-07-15 19:50:14 +02:00
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/* Reflow Oven Controller
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2021-10-10 20:40:40 +02:00
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*
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* Copyright (C) 2021 Mario Hüttel <mario.huettel@gmx.net>
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*
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* This file is part of the Reflow Oven Controller Project.
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*
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* The reflow oven controller is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* The Reflow Oven Control Firmware is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with the reflow oven controller project.
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* If not, see <http://www.gnu.org/licenses/>.
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*/
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2021-07-15 19:50:14 +02:00
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/**
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* @addtogroup hw-version-detect
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* @{
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*/
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2020-11-29 19:02:30 +01:00
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#include <reflow-controller/hw-version-detect.h>
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2020-12-01 21:00:23 +01:00
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#include <stm-periph/rcc-manager.h>
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2020-11-29 19:02:30 +01:00
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#include <stm32/stm32f4xx.h>
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2022-07-30 16:45:26 +02:00
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#if HW_REV_DETECT_PIN_LOW > HW_REV_DETECT_PIN_HIGH
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#error Configuration error for Hardware derection pins. Lowest position must be less than the highest pin position.
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#endif
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2020-11-29 19:02:30 +01:00
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enum hw_revision get_pcb_hardware_version(void)
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{
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uint8_t current_pin;
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2022-08-09 00:23:55 +02:00
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uint16_t port_bitmask = 0U; /* Use uint16_t because a port can have 16 IOs max. */
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const uint16_t highest_bit_mask = (1 << (HW_REV_DETECT_PIN_HIGH - HW_REV_DETECT_PIN_LOW));
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2020-11-29 19:02:30 +01:00
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static enum hw_revision revision = HW_REV_NOT_DETECTED;
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2021-10-23 21:18:32 +02:00
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/* If the revision has been previously detected,
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* just return it and don't do the whole detection stuff
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*/
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2020-11-29 19:02:30 +01:00
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if (revision != HW_REV_NOT_DETECTED)
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return revision;
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rcc_manager_enable_clock(&RCC->AHB1ENR, BITMASK_TO_BITNO(HW_REV_DETECT_RCC_FIELD));
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/* Setup the pins as input with pull up */
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for (current_pin = HW_REV_DETECT_PIN_LOW; current_pin <= HW_REV_DETECT_PIN_HIGH; current_pin++) {
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HW_REV_DETECT_GPIO->MODER &= MODER_DELETE(current_pin);
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HW_REV_DETECT_GPIO->PUPDR &= PUPDR_DELETE(current_pin);
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HW_REV_DETECT_GPIO->PUPDR |= PULLUP(current_pin);
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}
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2021-10-23 21:18:32 +02:00
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/* Loop again and read in the pin mask.
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* Because we use GND-Shorts on the pins to detect the version, the pins are read inverted.
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*/
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2020-11-29 19:02:30 +01:00
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for (current_pin = HW_REV_DETECT_PIN_LOW; current_pin <= HW_REV_DETECT_PIN_HIGH; current_pin++) {
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2021-01-01 17:28:38 +01:00
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port_bitmask >>= 1;
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2022-08-09 00:23:55 +02:00
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port_bitmask |= (HW_REV_DETECT_GPIO->IDR & (1 << current_pin)) ? 0x0 : highest_bit_mask;
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2020-11-29 19:02:30 +01:00
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}
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2021-10-23 21:18:32 +02:00
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/* Resolve the read in bitmask to a hardware version */
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2020-11-29 19:02:30 +01:00
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switch (port_bitmask) {
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case 0U:
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revision = HW_REV_V1_2;
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break;
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case 1U:
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revision = HW_REV_V1_3;
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break;
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2021-10-24 21:58:52 +02:00
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case 2U:
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revision = HW_REV_V1_3_1;
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break;
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2020-11-29 19:02:30 +01:00
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default:
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revision = HW_REV_ERROR;
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}
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rcc_manager_disable_clock(&RCC->AHB1ENR, BITMASK_TO_BITNO(HW_REV_DETECT_RCC_FIELD));
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return revision;
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}
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2021-07-15 19:50:14 +02:00
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/** @} */
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