2020-02-05 23:09:23 +01:00
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#include <uart/dma-ring-buffer.h>
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2020-02-09 19:13:37 +01:00
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#include <clock-enable-manager.h>
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2020-02-10 22:38:24 +01:00
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#include <stdbool.h>
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2020-02-05 23:09:23 +01:00
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2020-02-10 22:38:24 +01:00
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static int dma_ring_buffer_switch_clock_enable(uint8_t base_dma, bool clk_en)
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2020-02-09 19:13:37 +01:00
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{
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2020-02-10 22:38:24 +01:00
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int ret_val;
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int (*clk_func)(volatile uint32_t *, uint8_t);
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2020-02-09 19:13:37 +01:00
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2020-02-10 22:38:24 +01:00
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if (clk_en)
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clk_func = rcc_manager_enable_clock;
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else
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clk_func = rcc_manager_disable_clock;
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2020-02-09 19:13:37 +01:00
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2020-02-10 22:38:24 +01:00
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switch (base_dma) {
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2020-02-09 19:13:37 +01:00
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case 1:
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2020-02-10 22:38:24 +01:00
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ret_val = clk_func(&RCC->AHB1ENR, BITMASK_TO_BITNO(RCC_AHB1ENR_DMA1EN));
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2020-02-09 19:13:37 +01:00
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break;
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case 2:
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2020-02-10 22:38:24 +01:00
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ret_val = clk_func(&RCC->AHB1ENR, BITMASK_TO_BITNO(RCC_AHB1ENR_DMA2EN));
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2020-02-09 19:13:37 +01:00
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break;
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default:
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2020-02-10 22:38:24 +01:00
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ret_val = -1000;
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2020-02-09 19:13:37 +01:00
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break;
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}
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2020-02-10 22:38:24 +01:00
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return ret_val;
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}
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int dma_ring_buffer_periph_to_mem_initialize(struct dma_ring_buffer_to_mem *dma_buffer, uint8_t base_dma_id,
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DMA_Stream_TypeDef *dma_stream, size_t buffer_element_count, size_t element_size,
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void *data_buffer, void* src_reg, uint8_t dma_trigger_channel)
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{
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int ret_val = 0;
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if (!dma_buffer || !dma_stream || !data_buffer || !src_reg)
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return -1000;
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if (dma_trigger_channel > 7)
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return -1007;
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dma_buffer->base_dma_id = base_dma_id;
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ret_val = dma_ring_buffer_switch_clock_enable(base_dma_id, true);
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if (ret_val)
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return ret_val;
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2020-02-09 19:13:37 +01:00
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dma_buffer->dma = dma_stream;
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dma_buffer->get_idx = 0;
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dma_buffer->buffer_count = buffer_element_count;
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dma_buffer->data_ptr = data_buffer;
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2020-02-10 22:38:24 +01:00
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dma_buffer->element_size = element_size;
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2020-02-09 19:13:37 +01:00
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dma_stream->PAR = (uint32_t)src_reg;
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dma_stream->M0AR = (uint32_t)data_buffer;
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dma_stream->NDTR = buffer_element_count;
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dma_stream->NDTR = buffer_element_count;
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dma_stream->CR |= (dma_trigger_channel<<25) | DMA_SxCR_MINC | DMA_SxCR_CIRC | DMA_SxCR_EN;
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return 0;
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}
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2020-02-10 22:38:24 +01:00
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int dma_ring_buffer_periph_to_mem_get_data(struct dma_ring_buffer_to_mem *buff, const void **data_buff, size_t *len)
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2020-02-09 19:13:37 +01:00
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{
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int ret_code = 0;
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uint32_t ndtr;
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size_t put_idx;
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if (!buff || !data_buff || !len)
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return -1;
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ndtr = buff->dma->NDTR;
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put_idx = buff->buffer_count - ndtr;
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/* Check if wrap around */
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if (put_idx < buff->get_idx) {
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2020-02-10 22:38:24 +01:00
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*data_buff = &(((char *)buff->data_ptr)[buff->get_idx * buff->element_size]);
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2020-02-09 19:13:37 +01:00
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*len = buff->buffer_count - buff->get_idx;
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buff->get_idx = 0;
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ret_code = 1;
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} else if (put_idx > buff->get_idx) {
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2020-02-10 22:38:24 +01:00
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*data_buff = &(((char *)buff->data_ptr)[buff->get_idx * buff->element_size]);
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2020-02-09 19:13:37 +01:00
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*len = put_idx - buff->get_idx;
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buff->get_idx += *len;
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} else {
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/* No new data */
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*len = 0;
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}
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return ret_code;
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}
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2020-02-10 22:38:24 +01:00
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void dma_ring_buffer_periph_to_mem_stop(struct dma_ring_buffer_to_mem *buff)
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2020-02-09 19:13:37 +01:00
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{
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if (!buff || !buff->dma)
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return;
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buff->dma->CR = 0;
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buff->dma->NDTR = 0;
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buff->dma->M1AR = 0;
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buff->dma->FCR = 0;
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2020-02-10 22:38:24 +01:00
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dma_ring_buffer_switch_clock_enable(buff->base_dma_id, false);
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2020-02-09 19:13:37 +01:00
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}
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