2020-02-24 18:48:26 +01:00
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#ifndef __SHELL_UART_CONFIG_H__
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#define __SHELL_UART_CONFIG_H__
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#define SHELL_UART_RECEIVE_DMA_STREAM DMA2_Stream5
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#define SHELL_UART_SEND_DMA_STREAM DMA2_Stream7
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#define SHELL_UART_PERIPH USART1
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#define SHELL_UART_RCC_REG RCC->APB2ENR
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#define SHELL_UART_RCC_MASK RCC_APB2ENR_USART1EN
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#define SHELL_UART_RX_DMA_TRIGGER 4U
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#define SHELL_UART_TX_DMA_TRIGGER 4U
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2020-11-01 21:22:28 +01:00
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#if defined(DEBUGBUILD) || defined(UART_ON_DEBUG_HEADER)
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2020-02-24 18:48:26 +01:00
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#define SHELL_UART_PORT GPIOA
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#define SHELL_UART_PORT_RCC_MASK RCC_AHB1ENR_GPIOAEN
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#define SHELL_UART_RX_PIN 10
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#define SHELL_UART_TX_PIN 9
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#define SHELL_UART_RX_PIN_ALTFUNC 7
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#define SHELL_UART_TX_PIN_ALTFUNC 7
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#else
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#endif
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/* UART_DIV is 45.5625 => 115200 @ 84 MHz */
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#define SHELL_UART_DIV_FRACTION 9U /* Equals 9/16 = 0.5625 */
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#define SHELL_UART_DIV_MANTISSA 45U /* Equals 45 */
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#define SHELL_UART_BRR_REG_VALUE ((SHELL_UART_DIV_MANTISSA<<4) | SHELL_UART_DIV_FRACTION);
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#endif /* __SHELL_UART_CONFIG_H__ */
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