2021-07-15 19:50:14 +02:00
|
|
|
/* Reflow Oven Controller
|
|
|
|
*
|
|
|
|
* Copyright (C) 2021 Mario Hüttel <mario.huettel@gmx.net>
|
|
|
|
*
|
|
|
|
* This file is part of the Reflow Oven Controller Project.
|
|
|
|
*
|
|
|
|
* The reflow oven controller is free software: you can redistribute it and/or modify
|
|
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
|
|
* published by the Free Software Foundation.
|
|
|
|
*
|
|
|
|
* The Reflow Oven Control Firmware is distributed in the hope that it will be useful,
|
|
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
|
|
* GNU General Public License for more details.
|
|
|
|
*
|
|
|
|
* You should have received a copy of the GNU General Public License
|
|
|
|
* along with the reflow oven controller project.
|
|
|
|
* If not, see <http://www.gnu.org/licenses/>.
|
|
|
|
*/
|
|
|
|
|
|
|
|
/**
|
|
|
|
* @addtogroup hw-version-detect
|
|
|
|
* @{
|
|
|
|
*/
|
|
|
|
|
2020-11-29 19:02:30 +01:00
|
|
|
#include <reflow-controller/hw-version-detect.h>
|
2020-12-01 21:00:23 +01:00
|
|
|
#include <stm-periph/rcc-manager.h>
|
2020-11-29 19:02:30 +01:00
|
|
|
#include <stm32/stm32f4xx.h>
|
|
|
|
|
|
|
|
enum hw_revision get_pcb_hardware_version(void)
|
|
|
|
{
|
|
|
|
uint8_t current_pin;
|
|
|
|
uint16_t port_bitmask = 0U;
|
|
|
|
static enum hw_revision revision = HW_REV_NOT_DETECTED;
|
|
|
|
|
|
|
|
if (revision != HW_REV_NOT_DETECTED)
|
|
|
|
return revision;
|
|
|
|
|
|
|
|
rcc_manager_enable_clock(&RCC->AHB1ENR, BITMASK_TO_BITNO(HW_REV_DETECT_RCC_FIELD));
|
|
|
|
|
|
|
|
/* Setup the pins as input with pull up */
|
|
|
|
for (current_pin = HW_REV_DETECT_PIN_LOW; current_pin <= HW_REV_DETECT_PIN_HIGH; current_pin++) {
|
|
|
|
HW_REV_DETECT_GPIO->MODER &= MODER_DELETE(current_pin);
|
|
|
|
HW_REV_DETECT_GPIO->PUPDR &= PUPDR_DELETE(current_pin);
|
|
|
|
HW_REV_DETECT_GPIO->PUPDR |= PULLUP(current_pin);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Loop again and read in the pin mask */
|
|
|
|
for (current_pin = HW_REV_DETECT_PIN_LOW; current_pin <= HW_REV_DETECT_PIN_HIGH; current_pin++) {
|
2021-01-01 17:28:38 +01:00
|
|
|
port_bitmask >>= 1;
|
|
|
|
port_bitmask |= (HW_REV_DETECT_GPIO->IDR & (1 << current_pin)) ? 0x0 : 0x80;
|
2020-11-29 19:02:30 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
switch (port_bitmask) {
|
|
|
|
case 0U:
|
|
|
|
revision = HW_REV_V1_2;
|
|
|
|
break;
|
|
|
|
case 1U:
|
|
|
|
revision = HW_REV_V1_3;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
revision = HW_REV_ERROR;
|
|
|
|
}
|
|
|
|
|
|
|
|
rcc_manager_disable_clock(&RCC->AHB1ENR, BITMASK_TO_BITNO(HW_REV_DETECT_RCC_FIELD));
|
|
|
|
|
|
|
|
return revision;
|
|
|
|
}
|
2021-07-15 19:50:14 +02:00
|
|
|
|
|
|
|
/** @} */
|