Shorten wtchdog trigger interval to 1.25 seconds nominal. This will ensure the internal watchdog triggers before the external one
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df593e2ab2
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1300fe88a4
@ -126,7 +126,15 @@ enum analog_value_monitor {
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#define WATCHDOG_HALT_DEBUG (0)
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#endif
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#define WATCHDOG_PRESCALER 16
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/**
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* @brief Watchdog clock prescaler value
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*/
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#define WATCHDOG_PRESCALER (16)
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/**
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* @brief Watchdog reload value
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*/
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#define WATCHDOG_RELOAD_VALUE (2500)
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/**
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* @brief Minimum number of bytes that have to be free on the stack. If this is not the case, an error is detected
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@ -27,11 +27,19 @@
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/**
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* @brief Setup the watchdog for the safety controller
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* @param Prescaler to use for the 32 KHz LSI clock
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*
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* The watchdog timeout can be calculated with:
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* \f[ t = \frac{(\mathrm{RELOAD_VAL} + 1)\cdot \mathrm{PRESCALER}}{32000 } s\f]
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*
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* Valid prescaler values are: 4, 8, 16, 32, 64, 128, 256.
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* @param prescaler Prescaler to use for the 32 KHz LSI clock
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* @param reload_value Reload value to reload the timer with when reset. 0 to 0xFFF
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* @return 0 if successful
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* @return -1 if prescaler is wrong
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* @return -2 if a reload value > 0xFFF is selected. 0xFFF will be used in this case
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* @note Once the watchdog is enabled, it cannot be turned off!
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*/
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int watchdog_setup(uint8_t prescaler);
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int watchdog_setup(uint16_t prescaler, uint16_t reload_value);
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/**
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* @brief Reset watchdog counter
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@ -322,6 +322,7 @@ static const struct crc_monitor_register safety_adc_crc_regs[] = {
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static const struct crc_monitor_register misc_config_crc_regs[] = {
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/* Check clock tree settings */
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CRC_MON_REGISTER_ENTRY(RCC->CR, RCC_CR_PLLON | RCC_CR_HSEON | RCC_CR_PLLI2SON | RCC_CR_HSION, 4),
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CRC_MON_REGISTER_ENTRY(RCC->CSR, RCC_CSR_LSION, 4),
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CRC_MON_REGISTER_ENTRY(RCC->CFGR, RCC_CFGR_SWS | RCC_CFGR_HPRE | RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2, 4),
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CRC_MON_REGISTER_ENTRY(RCC->PLLCFGR, RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLP | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLM , 4),
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/* Check Flash settings */
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@ -972,7 +973,7 @@ void safety_controller_init(void)
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MEAS_ADC_SAFETY_FLAG_KEY);
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safety_adc_init();
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watchdog_setup(WATCHDOG_PRESCALER);
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(void)watchdog_setup(WATCHDOG_PRESCALER, WATCHDOG_RELOAD_VALUE);
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if (rcc_manager_get_reset_cause(false) & RCC_RESET_SOURCE_IWDG)
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safety_controller_report_error(ERR_FLAG_WTCHDG_FIRED);
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@ -42,9 +42,10 @@
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*/
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#define STM32_WATCHDOG_REGISTER_ACCESS_KEY 0x5555
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int watchdog_setup(uint8_t prescaler)
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int watchdog_setup(uint16_t prescaler, uint16_t reload_value)
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{
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uint32_t prescaler_reg_val;
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int ret = 0;
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/** - Activate the LSI oscillator */
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RCC->CSR |= RCC_CSR_LSION;
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@ -53,20 +54,24 @@ int watchdog_setup(uint8_t prescaler)
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while (!(RCC->CSR & RCC_CSR_LSIRDY))
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;
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if (prescaler == 4U)
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if (prescaler == 4U) {
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prescaler_reg_val = 0UL;
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else if (prescaler == 8U)
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} else if (prescaler == 8U) {
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prescaler_reg_val = 1UL;
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else if (prescaler == 16U)
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} else if (prescaler == 16U) {
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prescaler_reg_val = 2UL;
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else if (prescaler == 32U)
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} else if (prescaler == 32U) {
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prescaler_reg_val = 3UL;
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else if (prescaler == 64U)
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} else if (prescaler == 64U) {
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prescaler_reg_val = 4UL;
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else if (prescaler == 128U)
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} else if (prescaler == 128U) {
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prescaler_reg_val = 5UL;
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else
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} else if (prescaler == 256U) {
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prescaler_reg_val = 6UL;
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} else {
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prescaler_reg_val = 6UL;
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ret = -1;
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}
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/** - (De)activate the watchdog during debug access according to @ref WATCHDOG_HALT_DEBUG */
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if (WATCHDOG_HALT_DEBUG)
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@ -88,7 +93,11 @@ int watchdog_setup(uint8_t prescaler)
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while (IWDG->SR & IWDG_SR_RVU)
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;
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/** - Set reload value fixed to 0xFFF */
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/** - Set reload value */
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if (reload_value > 0xFFFu) {
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reload_value = 0xFFFFu;
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ret = -2;
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}
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IWDG->RLR = 0xFFFU;
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/** - Write enable key */
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@ -97,7 +106,7 @@ int watchdog_setup(uint8_t prescaler)
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/** - Do a first reset of the counter. This also locks the config regs */
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watchdog_ack(WATCHDOG_MAGIC_KEY);
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return 0;
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return ret;
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}
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int watchdog_ack(uint32_t magic)
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