mhu/reflow-oven-control-sw
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Fix style issues in STM peripheral drivers

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This commit is contained in:
Mario Hüttel 2022-07-16 12:46:52 +02:00
parent d5780500f3
commit 14ea4d22fe
9 changed files with 292 additions and 275 deletions
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2
stm-firmware/include/stm-periph/rng.h
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@ -33,7 +33,7 @@ enum random_number_error {
void random_number_gen_init(bool int_enable); void random_number_gen_init(bool int_enable);
void random_number_gen_deinit(); void random_number_gen_deinit(void);
void random_number_gen_reset(bool int_en); void random_number_gen_reset(bool int_en);

3
stm-firmware/stm-periph/backup-ram.c
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@ -46,7 +46,8 @@ void backup_ram_init(bool use_backup_regulator)
PWR->CSR |= PWR_CSR_BRE; PWR->CSR |= PWR_CSR_BRE;
/* Wait until regulator is ready */ /* Wait until regulator is ready */
while (!(PWR->CSR & PWR_CSR_BRR)); while (!(PWR->CSR & PWR_CSR_BRR))
;
} }
/* Enable clock for backup ram interface */ /* Enable clock for backup ram interface */

32
stm-firmware/stm-periph/dma-ring-buffer.c
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@ -37,11 +37,10 @@ static size_t calculate_ring_buffer_fill_level(size_t buffer_size, size_t get_id
{ {
size_t fill_level; size_t fill_level;
if (put_idx >= get_idx) { if (put_idx >= get_idx)
fill_level = (put_idx - get_idx); fill_level = (put_idx - get_idx);
} else { else
fill_level = buffer_size - get_idx + put_idx; fill_level = buffer_size - get_idx + put_idx;
}
return fill_level; return fill_level;
} }
@ -49,7 +48,7 @@ static size_t calculate_ring_buffer_fill_level(size_t buffer_size, size_t get_id
static int dma_ring_buffer_switch_clock_enable(uint8_t base_dma, bool clk_en) static int dma_ring_buffer_switch_clock_enable(uint8_t base_dma, bool clk_en)
{ {
int ret_val; int ret_val;
int (*clk_func)(volatile uint32_t *, uint8_t); int (*clk_func)(volatile uint32_t *reg, uint8_t bit_no);
if (clk_en) if (clk_en)
clk_func = rcc_manager_enable_clock; clk_func = rcc_manager_enable_clock;
@ -72,8 +71,9 @@ static int dma_ring_buffer_switch_clock_enable(uint8_t base_dma, bool clk_en)
} }
int dma_ring_buffer_periph_to_mem_initialize(struct dma_ring_buffer_to_mem *dma_buffer, uint8_t base_dma_id, int dma_ring_buffer_periph_to_mem_initialize(struct dma_ring_buffer_to_mem *dma_buffer, uint8_t base_dma_id,
DMA_Stream_TypeDef *dma_stream, size_t buffer_element_count, size_t element_size, DMA_Stream_TypeDef *dma_stream, size_t buffer_element_count,
volatile void *data_buffer, void* src_reg, uint8_t dma_trigger_channel) size_t element_size, volatile void *data_buffer,
void *src_reg, uint8_t dma_trigger_channel)
{ {
int ret_val = 0; int ret_val = 0;
@ -106,7 +106,8 @@ int dma_ring_buffer_periph_to_mem_initialize(struct dma_ring_buffer_to_mem *dma_
return 0; return 0;
} }
int dma_ring_buffer_periph_to_mem_get_data(struct dma_ring_buffer_to_mem *buff, const volatile void **data_buff, size_t *len) int dma_ring_buffer_periph_to_mem_get_data(struct dma_ring_buffer_to_mem *buff, const volatile void **data_buff,
size_t *len)
{ {
int ret_code = 0; int ret_code = 0;
uint32_t ndtr; uint32_t ndtr;
@ -167,7 +168,10 @@ int dma_ring_buffer_periph_to_mem_fill_level(struct dma_ring_buffer_to_mem *buff
return 0; return 0;
} }
int dma_ring_buffer_mem_to_periph_initialize(struct dma_ring_buffer_to_periph *dma_buffer, uint8_t base_dma_id, DMA_Stream_TypeDef *dma_stream, size_t buffer_element_count, size_t element_size, volatile void *data_buffer, uint8_t dma_trigger_channel, void *dest_reg) int dma_ring_buffer_mem_to_periph_initialize(struct dma_ring_buffer_to_periph *dma_buffer, uint8_t base_dma_id,
DMA_Stream_TypeDef *dma_stream, size_t buffer_element_count,
size_t element_size, volatile void *data_buffer,
uint8_t dma_trigger_channel, void *dest_reg)
{ {
if (!dma_buffer || !dma_stream || !data_buffer || !dest_reg) if (!dma_buffer || !dma_stream || !data_buffer || !dest_reg)
return -1000; return -1000;
@ -221,7 +225,8 @@ static void queue_or_start_dma_transfer(struct dma_ring_buffer_to_periph *buff)
buff->dma->CR |= DMA_SxCR_EN; buff->dma->CR |= DMA_SxCR_EN;
} }
int dma_ring_buffer_mem_to_periph_insert_data(struct dma_ring_buffer_to_periph *buff, const void *data_to_insert, size_t count) int dma_ring_buffer_mem_to_periph_insert_data(struct dma_ring_buffer_to_periph *buff, const void *data_to_insert,
size_t count)
{ {
int ret = 0; int ret = 0;
size_t free_item_count; size_t free_item_count;
@ -234,7 +239,8 @@ int dma_ring_buffer_mem_to_periph_insert_data(struct dma_ring_buffer_to_periph *
return -1000; return -1000;
/* Check if data fits into buffer minus one element. If not: try full-1 buffer and rest /* Check if data fits into buffer minus one element. If not: try full-1 buffer and rest
* Buffer is not allowed to be completely full, because I cannot ddifferentiate a full buffer from a completely empty one * Buffer is not allowed to be completely full, because I cannot ddifferentiate a full buffer from a
* completely empty one
*/ */
if (count >= buff->buffer_count) { if (count >= buff->buffer_count) {
ret = dma_ring_buffer_mem_to_periph_insert_data(buff, data_to_insert, buff->buffer_count - 1); ret = dma_ring_buffer_mem_to_periph_insert_data(buff, data_to_insert, buff->buffer_count - 1);
@ -247,7 +253,9 @@ int dma_ring_buffer_mem_to_periph_insert_data(struct dma_ring_buffer_to_periph *
/* Wait for buffer to be able to handle input */ /* Wait for buffer to be able to handle input */
do { do {
free_item_count = buff->buffer_count - calculate_ring_buffer_fill_level(buff->buffer_count, buff->dma_get_idx_current, buff->sw_put_idx); free_item_count = buff->buffer_count -
calculate_ring_buffer_fill_level(buff->buffer_count, buff->dma_get_idx_current,
buff->sw_put_idx);
} while (free_item_count < count+1); } while (free_item_count < count+1);
/* Fillup buffer (max is buffer end, wrap around afterwards) */ /* Fillup buffer (max is buffer end, wrap around afterwards) */
@ -261,7 +269,7 @@ int dma_ring_buffer_mem_to_periph_insert_data(struct dma_ring_buffer_to_periph *
buff->sw_put_idx += count; buff->sw_put_idx += count;
/* If buffer is used up to last element, set put index to beginning */ /* If buffer is used up to last element, set put index to beginning */
if(buff->sw_put_idx >= buff->buffer_count) if (buff->sw_put_idx >= buff->buffer_count)
buff->sw_put_idx = 0; buff->sw_put_idx = 0;
} else { } else {
/* Fill up to end of buffer and fill rest after wrap around */ /* Fill up to end of buffer and fill rest after wrap around */

6
stm-firmware/stm-periph/option-bytes.c
View File

@ -76,12 +76,14 @@ int stm_option_bytes_program(const struct option_bytes *opts)
reg |= (opts->read_protection << 8) & FLASH_OPTCR_RDP; reg |= (opts->read_protection << 8) & FLASH_OPTCR_RDP;
reg |= (opts->wdg_sw << 5) & FLASH_OPTCR_WDG_SW; reg |= (opts->wdg_sw << 5) & FLASH_OPTCR_WDG_SW;
while (FLASH->SR & FLASH_SR_BSY); while (FLASH->SR & FLASH_SR_BSY)
;
FLASH->OPTCR = reg; FLASH->OPTCR = reg;
FLASH->OPTCR |= FLASH_OPTCR_OPTSTRT; FLASH->OPTCR |= FLASH_OPTCR_OPTSTRT;
__DSB(); __DSB();
while (FLASH->SR & FLASH_SR_BSY); while (FLASH->SR & FLASH_SR_BSY)
;
FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK; FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK;

6
stm-firmware/stm-periph/rcc-manager.c
View File

@ -95,9 +95,8 @@ int rcc_manager_enable_clock(volatile uint32_t *rcc_enable_register, uint8_t bit
int ret_val = 0; int ret_val = 0;
struct rcc_enable_count *entry; struct rcc_enable_count *entry;
if (!rcc_enable_register || bit_no > 31) { if (!rcc_enable_register || bit_no > 31)
return -1000; return -1000;
}
/* Enable the clock in any case, no matter what follows */ /* Enable the clock in any case, no matter what follows */
*rcc_enable_register |= (1U<<bit_no); *rcc_enable_register |= (1U<<bit_no);
@ -132,9 +131,8 @@ int rcc_manager_disable_clock(volatile uint32_t *rcc_enable_register, uint8_t bi
int ret_val = -1; int ret_val = -1;
struct rcc_enable_count *entry; struct rcc_enable_count *entry;
if (!rcc_enable_register || bit_no > 31) { if (!rcc_enable_register || bit_no > 31)
return -1000; return -1000;
}
entry = search_enable_entry_in_list(rcc_enable_register, bit_no); entry = search_enable_entry_in_list(rcc_enable_register, bit_no);

4
stm-firmware/stm-periph/rng.c
View File

@ -30,7 +30,7 @@ void random_number_gen_init(bool int_enable)
random_number_gen_reset(int_enable); random_number_gen_reset(int_enable);
} }
void random_number_gen_deinit() void random_number_gen_deinit(void)
{ {
RNG->CR = 0; RNG->CR = 0;
__DSB(); __DSB();
@ -66,5 +66,5 @@ enum random_number_error random_number_gen_get_number(uint32_t *random_number, b
*random_number = RNG->DR; *random_number = RNG->DR;
/* Return from function with proper status */ /* Return from function with proper status */
return (value_ready ? RNG_ERROR_OK : RNG_ERROR_NOT_READY); return value_ready ? RNG_ERROR_OK : RNG_ERROR_NOT_READY;
} }

47
stm-firmware/stm-periph/spi.c
View File

@ -1,22 +1,22 @@
/* Reflow Oven Controller /* Reflow Oven Controller
* *
* Copyright (C) 2021 Mario Hüttel <mario.huettel@gmx.net> * Copyright (C) 2021 Mario Hüttel <mario.huettel@gmx.net>
* *
* This file is part of the Reflow Oven Controller Project. * This file is part of the Reflow Oven Controller Project.
* *
* The reflow oven controller is free software: you can redistribute it and/or modify * The reflow oven controller is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as * it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation. * published by the Free Software Foundation.
* *
* The Reflow Oven Control Firmware is distributed in the hope that it will be useful, * The Reflow Oven Control Firmware is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of * but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details. * GNU General Public License for more details.
* *
* You should have received a copy of the GNU General Public License * You should have received a copy of the GNU General Public License
* along with the reflow oven controller project. * along with the reflow oven controller project.
* If not, see <http://www.gnu.org/licenses/>. * If not, see <http://www.gnu.org/licenses/>.
*/ */
#include <stm-periph/spi.h> #include <stm-periph/spi.h>
#include <helper-macros/helper-macros.h> #include <helper-macros/helper-macros.h>
@ -65,7 +65,8 @@ static struct stm_spi_dev *spi_handle_to_struct(stm_spi_handle handle)
return dev; return dev;
} }
stm_spi_handle spi_init(struct stm_spi_dev *spi_dev_struct, SPI_TypeDef *spi_regs, const struct stm_spi_settings *settings) stm_spi_handle spi_init(struct stm_spi_dev *spi_dev_struct, SPI_TypeDef *spi_regs,
const struct stm_spi_settings *settings)
{ {
stm_spi_handle ret_handle = NULL; stm_spi_handle ret_handle = NULL;
uint32_t reg_val; uint32_t reg_val;
@ -131,10 +132,14 @@ void spi_deinit(stm_spi_handle handle)
static uint8_t transfer_byte(uint8_t byte, struct stm_spi_dev *dev) static uint8_t transfer_byte(uint8_t byte, struct stm_spi_dev *dev)
{ {
while (dev->spi_regs->SR & SPI_SR_BSY); while (dev->spi_regs->SR & SPI_SR_BSY)
;
dev->spi_regs->DR = (uint16_t)byte; dev->spi_regs->DR = (uint16_t)byte;
__DSB(); __DSB();
while((dev->spi_regs->SR & SPI_SR_BSY) || !(dev->spi_regs->SR & SPI_SR_TXE));
while ((dev->spi_regs->SR & SPI_SR_BSY) || !(dev->spi_regs->SR & SPI_SR_TXE))
;
return (uint8_t)dev->spi_regs->DR; return (uint8_t)dev->spi_regs->DR;
} }

451
stm-firmware/stm-periph/uart.c
View File

@ -1,224 +1,227 @@
/* Reflow Oven Controller /* Reflow Oven Controller
* *
* Copyright (C) 2020 Mario Hüttel <mario.huettel@gmx.net> * Copyright (C) 2020 Mario Hüttel <mario.huettel@gmx.net>
* *
* This file is part of the Reflow Oven Controller Project. * This file is part of the Reflow Oven Controller Project.
* *
* The reflow oven controller is free software: you can redistribute it and/or modify * The reflow oven controller is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as * it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation. * published by the Free Software Foundation.
* *
* The Reflow Oven Control Firmware is distributed in the hope that it will be useful, * The Reflow Oven Control Firmware is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of * but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details. * GNU General Public License for more details.
* *
* You should have received a copy of the GNU General Public License * You should have received a copy of the GNU General Public License
* along with the reflow oven controller project. * along with the reflow oven controller project.
* If not, see <http://www.gnu.org/licenses/>. * If not, see <http://www.gnu.org/licenses/>.
*/ */
#include <stm-periph/uart.h> #include <stm-periph/uart.h>
#include <stm32/stm32f4xx.h> #include <stm32/stm32f4xx.h>
#include <stm-periph/rcc-manager.h> #include <stm-periph/rcc-manager.h>
#include <stm-periph/stm32-gpio-macros.h> #include <stm-periph/stm32-gpio-macros.h>
#include <stm-periph/dma-ring-buffer.h> #include <stm-periph/dma-ring-buffer.h>
#include <string.h> #include <string.h>
int uart_init(struct stm_uart *uart) int uart_init(struct stm_uart *uart)
{ {
int ret_val = 0; int ret_val = 0;
uint32_t cr3 = 0; uint32_t cr3 = 0;
uint32_t cr1 = 0; uint32_t cr1 = 0;
if (!uart) if (!uart)
return -1000; return -1000;
rcc_manager_enable_clock(uart->rcc_reg, uart->rcc_bit_no); rcc_manager_enable_clock(uart->rcc_reg, uart->rcc_bit_no);
/* Reset all config regs */ /* Reset all config regs */
uart->uart_dev->CR1 = uart->uart_dev->CR2 = uart->uart_dev->CR3 = 0UL; uart->uart_dev->CR1 = uart->uart_dev->CR2 = uart->uart_dev->CR3 = 0UL;
/* Set baud rate */ /* Set baud rate */
uart->uart_dev->BRR = uart->brr_val; uart->uart_dev->BRR = uart->brr_val;
/* If DMA buffers are present, configure for DMA use */ /* If DMA buffers are present, configure for DMA use */
if (uart->dma_rx_buff && uart->rx) { if (uart->dma_rx_buff && uart->rx) {
cr3 |= USART_CR3_DMAR; cr3 |= USART_CR3_DMAR;
ret_val = dma_ring_buffer_periph_to_mem_initialize(&uart->rx_ring_buff, ret_val = dma_ring_buffer_periph_to_mem_initialize(&uart->rx_ring_buff,
uart->base_dma_num, uart->base_dma_num,
uart->dma_rx_stream, uart->dma_rx_stream,
uart->rx_buff_count, uart->rx_buff_count,
1U, 1U,
uart->dma_rx_buff, uart->dma_rx_buff,
(char *)&uart->uart_dev->DR, (char *)&uart->uart_dev->DR,
uart->dma_rx_trigger_channel); uart->dma_rx_trigger_channel);
if (ret_val) if (ret_val)
return ret_val; return ret_val;
} }
if (uart->dma_tx_buff && uart->tx) { if (uart->dma_tx_buff && uart->tx) {
ret_val = dma_ring_buffer_mem_to_periph_initialize(&uart->tx_ring_buff, ret_val = dma_ring_buffer_mem_to_periph_initialize(&uart->tx_ring_buff,
uart->base_dma_num, uart->base_dma_num,
uart->dma_tx_stream, uart->dma_tx_stream,
uart->tx_buff_count, uart->tx_buff_count,
1U, 1U,
uart->dma_tx_buff, uart->dma_tx_buff,
uart->dma_tx_trigger_channel, uart->dma_tx_trigger_channel,
(void *)&uart->uart_dev->DR); (void *)&uart->uart_dev->DR);
if (ret_val) if (ret_val)
return ret_val; return ret_val;
cr3 |= USART_CR3_DMAT; cr3 |= USART_CR3_DMAT;
} }
uart->uart_dev->CR3 = cr3; uart->uart_dev->CR3 = cr3;
if (uart->tx) if (uart->tx)
cr1 |= USART_CR1_TE; cr1 |= USART_CR1_TE;
if (uart->rx) if (uart->rx)
cr1 |= USART_CR1_RE; cr1 |= USART_CR1_RE;
/* Enable uart */ /* Enable uart */
cr1 |= USART_CR1_UE; cr1 |= USART_CR1_UE;
uart->uart_dev->CR1 = cr1; uart->uart_dev->CR1 = cr1;
return 0; return 0;
} }
void uart_change_brr(struct stm_uart *uart, uint32_t brr) void uart_change_brr(struct stm_uart *uart, uint32_t brr)
{ {
if (!uart || !uart->uart_dev) if (!uart || !uart->uart_dev)
return; return;
uart->brr_val = brr; uart->brr_val = brr;
uart->uart_dev->BRR = brr; uart->uart_dev->BRR = brr;
} }
uint32_t uart_get_brr(struct stm_uart *uart) uint32_t uart_get_brr(struct stm_uart *uart)
{ {
if (!uart || !uart->uart_dev) if (!uart || !uart->uart_dev)
return 0; return 0;
return uart->brr_val; return uart->brr_val;
} }
void uart_disable(struct stm_uart *uart) void uart_disable(struct stm_uart *uart)
{ {
if (!uart) if (!uart)
return; return;
uart->uart_dev->CR1 = 0; uart->uart_dev->CR1 = 0;
uart->uart_dev->CR2 = 0; uart->uart_dev->CR2 = 0;
uart->uart_dev->CR3 = 0; uart->uart_dev->CR3 = 0;
if (uart->rx && uart->dma_rx_buff) if (uart->rx && uart->dma_rx_buff)
dma_ring_buffer_periph_to_mem_stop(&uart->rx_ring_buff); dma_ring_buffer_periph_to_mem_stop(&uart->rx_ring_buff);
if (uart->dma_tx_buff && uart->tx) if (uart->dma_tx_buff && uart->tx)
dma_ring_buffer_mem_to_periph_stop(&uart->tx_ring_buff); dma_ring_buffer_mem_to_periph_stop(&uart->tx_ring_buff);
rcc_manager_disable_clock(uart->rcc_reg, uart->rcc_bit_no); rcc_manager_disable_clock(uart->rcc_reg, uart->rcc_bit_no);
} }
void uart_send_char(struct stm_uart *uart, char c) void uart_send_char(struct stm_uart *uart, char c)
{ {
if (!uart || !uart->uart_dev) if (!uart || !uart->uart_dev)
return; return;
while(!(uart->uart_dev->SR & USART_SR_TXE)); while (!(uart->uart_dev->SR & USART_SR_TXE))
uart->uart_dev->DR = c; ;
}
uart->uart_dev->DR = c;
void uart_send_array(struct stm_uart *uart, const char *data, uint32_t len) }
{
uint32_t i; void uart_send_array(struct stm_uart *uart, const char *data, uint32_t len)
{
for (i = 0; i < len; i++) uint32_t i;
uart_send_char(uart, data[i]);
} for (i = 0; i < len; i++)
uart_send_char(uart, data[i]);
void uart_send_string(struct stm_uart *uart, const char *string) }
{
int i; void uart_send_string(struct stm_uart *uart, const char *string)
{
for (i = 0; string[i] != '\0'; i++) int i;
uart_send_char(uart, string[i]);
} for (i = 0; string[i] != '\0'; i++)
uart_send_char(uart, string[i]);
void uart_send_array_with_dma(struct stm_uart *uart, const char *data, uint32_t len) }
{
if (!uart || !uart->dma_tx_buff) void uart_send_array_with_dma(struct stm_uart *uart, const char *data, uint32_t len)
return; {
if (!uart || !uart->dma_tx_buff)
dma_ring_buffer_mem_to_periph_insert_data(&uart->tx_ring_buff, data, len); return;
}
dma_ring_buffer_mem_to_periph_insert_data(&uart->tx_ring_buff, data, len);
void uart_send_string_with_dma(struct stm_uart *uart, const char *string) }
{
size_t len; void uart_send_string_with_dma(struct stm_uart *uart, const char *string)
{
len = strlen(string); size_t len;
uart_send_array_with_dma(uart, string, (uint32_t)len);
} len = strlen(string);
uart_send_array_with_dma(uart, string, (uint32_t)len);
int uart_receive_data_with_dma(struct stm_uart *uart, const char **data, size_t *len) }
{
if (!uart) int uart_receive_data_with_dma(struct stm_uart *uart, const char **data, size_t *len)
return -1000; {
if (!uart)
return dma_ring_buffer_periph_to_mem_get_data(&uart->rx_ring_buff, (const volatile void **)data, len); return -1000;
}
return dma_ring_buffer_periph_to_mem_get_data(&uart->rx_ring_buff, (const volatile void **)data, len);
char uart_get_char(struct stm_uart *uart) }
{
if (!uart) char uart_get_char(struct stm_uart *uart)
return 0; {
/* Wait for data to be available */ if (!uart)
while (!(uart->uart_dev->SR & USART_SR_RXNE)); return 0;
/* Wait for data to be available */
return (char)uart->uart_dev->DR; while (!(uart->uart_dev->SR & USART_SR_RXNE))
} ;
int uart_check_rx_avail(struct stm_uart *uart) return (char)uart->uart_dev->DR;
{ }
if (!uart)
return 0; int uart_check_rx_avail(struct stm_uart *uart)
{
if (uart->uart_dev->SR & USART_SR_RXNE) if (!uart)
return 1; return 0;
else
return 0; if (uart->uart_dev->SR & USART_SR_RXNE)
} return 1;
else
void uart_tx_dma_complete_int_callback(struct stm_uart *uart) return 0;
{ }
if (!uart)
return; void uart_tx_dma_complete_int_callback(struct stm_uart *uart)
{
dma_ring_buffer_mem_to_periph_int_callback(&uart->tx_ring_buff); if (!uart)
} return;
size_t uart_dma_tx_queue_avail(struct stm_uart *uart) dma_ring_buffer_mem_to_periph_int_callback(&uart->tx_ring_buff);
{ }
size_t fill_level = 0UL;
size_t uart_dma_tx_queue_avail(struct stm_uart *uart)
if (!uart) {
return 0UL; size_t fill_level = 0UL;
(void)dma_ring_buffer_mem_to_periph_fill_level(&uart->tx_ring_buff, &fill_level); if (!uart)
return 0UL;
return fill_level;
} (void)dma_ring_buffer_mem_to_periph_fill_level(&uart->tx_ring_buff, &fill_level);
size_t uart_dma_rx_queue_avail(struct stm_uart *uart) return fill_level;
{ }
size_t fill_level = 0UL;
size_t uart_dma_rx_queue_avail(struct stm_uart *uart)
if (!uart) {
return 0UL; size_t fill_level = 0UL;
(void)dma_ring_buffer_periph_to_mem_fill_level(&uart->rx_ring_buff, &fill_level); if (!uart)
return 0UL;
return fill_level;
} (void)dma_ring_buffer_periph_to_mem_fill_level(&uart->rx_ring_buff, &fill_level);
return fill_level;
}

16
stm-firmware/stm-periph/unique-id.c
View File

@ -50,16 +50,16 @@ void stm_cpuid_get(uint8_t *implementer, uint8_t *variant, uint16_t *part_no, ui
cpuid = SCB->CPUID; cpuid = SCB->CPUID;
if (implementer) { if (implementer)
*implementer = (uint8_t)((cpuid >> 24) & 0xFFU); *implementer = (uint8_t)((cpuid >> 24) & 0xFFU);
}
if (variant) { if (variant)
*variant = (uint8_t)((cpuid >> 20) & 0x0FU); *variant = (uint8_t)((cpuid >> 20) & 0x0FU);
}
if (part_no) { if (part_no)
*part_no = (uint16_t)((cpuid >> 4) & 0x0FFFU); *part_no = (uint16_t)((cpuid >> 4) & 0x0FFFU);
}
if (rev) { if (rev)
*rev = (uint8_t)(cpuid & 0x0FU); *rev = (uint8_t)(cpuid & 0x0FU);
}
} }