mhu/reflow-oven-control-sw
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Make Uart driver universal

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This commit is contained in:
Mario Hüttel
2020-02-24 18:50:09 +01:00
parent 4bc85d474f
commit 5012b726cd
6 changed files with 208 additions and 104 deletions
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165
stm-firmware/stm-periph/uart.c
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@@ -25,99 +25,150 @@
#include <stm-periph/dma-ring-buffer.h>
#include <string.h>
static struct dma_ring_buffer_to_mem ring_buff_rx;
static struct dma_ring_buffer_to_periph ring_buff_tx;
static char uart_rx_buffer[64];
static char uart_tx_buffer[256];
#ifdef DEBUGBUILD
static inline void uart_gpio_config()
int uart_init(struct stm_uart *uart)
{
rcc_manager_enable_clock(&RCC->AHB1ENR, BITMASK_TO_BITNO(UART_PORT_RCC_MASK));
UART_PORT->MODER &= MODER_DELETE(UART_TX_PIN) & MODER_DELETE(UART_RX_PIN);
UART_PORT->MODER |= ALTFUNC(UART_RX_PIN) | ALTFUNC(UART_TX_PIN);
SETAF(UART_PORT, UART_RX_PIN, UART_RX_PIN_ALTFUNC);
SETAF(UART_PORT, UART_TX_PIN, UART_TX_PIN_ALTFUNC);
}
#endif
int ret_val = 0;
uint32_t cr3 = 0;
uint32_t cr1 = 0;
void uart_init_with_dma()
{
rcc_manager_enable_clock(&RCC->APB2ENR, BITMASK_TO_BITNO(UART_RCC_MASK));
#ifdef DEBUGBUILD
uart_gpio_config();
#endif
UART_PERIPH->BRR = UART_BRR_REG_VALUE;
UART_PERIPH->CR3 = USART_CR3_DMAR | USART_CR3_DMAT;
UART_PERIPH->CR1 = USART_CR1_TE | USART_CR1_RE | USART_CR1_UE;
if (!uart)
return -1000;
dma_ring_buffer_periph_to_mem_initialize(&ring_buff_rx, 2, UART_RECEIVE_DMA_STREAM, sizeof(uart_rx_buffer), 1U,
uart_rx_buffer, (char *)&UART_PERIPH->DR, 4);
dma_ring_buffer_mem_to_periph_initialize(&ring_buff_tx, 2, UART_SEND_DMA_STREAM, sizeof(uart_tx_buffer), 1U,
uart_tx_buffer, 4U, (void *)&UART_PERIPH->DR);
rcc_manager_enable_clock(uart->rcc_reg, uart->rcc_bit_no);
NVIC_EnableIRQ(DMA2_Stream7_IRQn);
/* Reset all config regs */
uart->uart_dev->CR1 = uart->uart_dev->CR2 = uart->uart_dev->CR3 = 0UL;
/* Set baud rate */
uart->uart_dev->BRR = uart->brr_val;
/* If DMA buffers are present, configure for DMA use */
if (uart->dma_rx_buff && uart->rx) {
cr3 |= USART_CR3_DMAR;
ret_val = dma_ring_buffer_periph_to_mem_initialize(&uart->rx_ring_buff,
uart->base_dma_num,
uart->dma_rx_stream,
uart->rx_buff_count,
1U,
uart->dma_rx_buff,
(char *)&uart->uart_dev->DR,
uart->dma_rx_trigger_channel);
if (ret_val)
return ret_val;
}
if (uart->dma_tx_buff && uart->tx) {
ret_val = dma_ring_buffer_mem_to_periph_initialize(&uart->tx_ring_buff,
uart->base_dma_num,
uart->dma_tx_stream,
uart->tx_buff_count,
1U,
uart->dma_tx_buff,
uart->dma_tx_trigger_channel,
(void *)&uart->uart_dev->DR);
if (ret_val)
return ret_val;
cr3 |= USART_CR3_DMAT;
}
uart->uart_dev->CR3 = cr3;
if (uart->tx)
cr1 |= USART_CR1_TE;
if (uart->rx)
cr1 |= USART_CR1_RE;
/* Enable uart */
cr1 |= USART_CR1_UE;
uart->uart_dev->CR1 = cr1;
return 0;
}
void uart_disable()
void uart_disable(struct stm_uart *uart)
{
UART_PERIPH->CR1 = 0;
UART_PERIPH->CR2 = 0;
UART_PERIPH->CR3 = 0;
dma_ring_buffer_periph_to_mem_stop(&ring_buff_rx);
dma_ring_buffer_mem_to_periph_stop(&ring_buff_tx);
#ifdef DEBUGBUILD
rcc_manager_disable_clock(&RCC->AHB1ENR, BITMASK_TO_BITNO(UART_PORT_RCC_MASK));
#endif
rcc_manager_disable_clock(&RCC->APB2ENR, BITMASK_TO_BITNO(UART_RCC_MASK));
if (!uart)
return;
uart->uart_dev->CR1 = 0;
uart->uart_dev->CR2 = 0;
uart->uart_dev->CR3 = 0;
if (uart->rx && uart->dma_rx_buff)
dma_ring_buffer_periph_to_mem_stop(&uart->rx_ring_buff);
if (uart->dma_tx_buff && uart->tx)
dma_ring_buffer_mem_to_periph_stop(&uart->tx_ring_buff);
rcc_manager_disable_clock(uart->rcc_reg, uart->rcc_bit_no);
}
void uart_send_char(char c)
void uart_send_char(struct stm_uart *uart, char c)
{
while(!(UART_PERIPH->SR & USART_SR_TXE));
UART_PERIPH->DR = c;
if (!uart || !uart->uart_dev)
return;
while(!(uart->uart_dev->SR & USART_SR_TXE));
uart->uart_dev->DR = c;
}
void uart_send_array(const char *data, uint32_t len)
void uart_send_array(struct stm_uart *uart, const char *data, uint32_t len)
{
uint32_t i;
for (i = 0; i < len; i++)
uart_send_char(data[i]);
uart_send_char(uart, data[i]);
}
void uart_send_string(const char *string)
void uart_send_string(struct stm_uart *uart, const char *string)
{
int i;
for (i = 0; string[i] != '\0'; i++)
uart_send_char(string[i]);
uart_send_char(uart, string[i]);
}
void uart_send_array_with_dma(const char *data, uint32_t len)
void uart_send_array_with_dma(struct stm_uart *uart, const char *data, uint32_t len)
{
dma_ring_buffer_mem_to_periph_insert_data(&ring_buff_tx, data, len);
if (!uart || !uart->dma_tx_buff)
return;
dma_ring_buffer_mem_to_periph_insert_data(&uart->tx_ring_buff, data, len);
}
void uart_send_string_with_dma(const char *string)
void uart_send_string_with_dma(struct stm_uart *uart, const char *string)
{
size_t len;
len = strlen(string);
uart_send_array_with_dma(string, (uint32_t)len);
uart_send_array_with_dma(uart, string, (uint32_t)len);
}
int uart_receive_data_with_dma(const char **data, size_t *len)
int uart_receive_data_with_dma(struct stm_uart *uart, const char **data, size_t *len)
{
return dma_ring_buffer_periph_to_mem_get_data(&ring_buff_rx, (const volatile void **)data, len);
if (!uart)
return -1000;
return dma_ring_buffer_periph_to_mem_get_data(&uart->rx_ring_buff, (const volatile void **)data, len);
}
void DMA2_Stream7_IRQHandler()
int uart_check_rx_avail(struct stm_uart *uart)
{
uint32_t hisr = DMA2->HISR;
DMA2->HIFCR = hisr;
if (!uart)
return 0;
if (hisr & DMA_HISR_TCIF7) {
dma_ring_buffer_mem_to_periph_int_callback(&ring_buff_tx);
}
if (uart->uart_dev->SR & USART_SR_RXNE)
return 1;
else
return 0;
}
void uart_tx_dma_complete_int_callback(struct stm_uart *uart)
{
if (!uart)
return;
dma_ring_buffer_mem_to_periph_int_callback(&uart->tx_ring_buff);
}