Fix bugs in settings saving
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6c92048de5
commit
543127b187
@ -611,6 +611,15 @@ DRESULT sdio_disk_read(BYTE *buff, DWORD sector, UINT count){
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uint32_t sdio_status;
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uint32_t sdio_status;
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uint32_t fifo;
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uint32_t fifo;
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uint32_t counter;
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uint32_t counter;
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int err;
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union sdio_status_conv status;
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do {
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err = sdio_check_status_register_cmd13(card_info.rca, &status.value);
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if (err)
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return RES_ERROR;
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} while (status.statusstruct.CURRENT_STATE != CURRENT_STATE_TRAN);
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addr = (card_info.type == SD_V2_HC ? (sector) : (sector*512));
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addr = (card_info.type == SD_V2_HC ? (sector) : (sector*512));
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for (; count > 0; count--) {
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for (; count > 0; count--) {
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@ -633,7 +642,8 @@ DRESULT sdio_disk_read(BYTE *buff, DWORD sector, UINT count){
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SDIO->DCTRL = (BLOCKSIZE<<4) | SDIO_DCTRL_DTDIR | /*SDIO_DCTRL_DMAEN |*/ SDIO_DCTRL_DTEN;
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SDIO->DCTRL = (BLOCKSIZE<<4) | SDIO_DCTRL_DTDIR | /*SDIO_DCTRL_DMAEN |*/ SDIO_DCTRL_DTEN;
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/* Init Transfer */
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/* Init Transfer */
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if (sdio_send_read_block_cmd17(addr)) {
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err = sdio_send_read_block_cmd17(addr);
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if (err) {
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return RES_ERROR;
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return RES_ERROR;
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}
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}
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@ -14,7 +14,7 @@
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//Initial Transfer CLK (ca. 400kHz)
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//Initial Transfer CLK (ca. 400kHz)
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#define INITCLK 140 //120
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#define INITCLK 140 //120
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//Working CLK (Maximum)
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//Working CLK (Maximum)
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#define WORKCLK 45 //0
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#define WORKCLK 50 //0
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//Data Timeout in CLK Cycles
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//Data Timeout in CLK Cycles
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#define DTIMEOUT 0x3000 //150
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#define DTIMEOUT 0x3000 //150
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//DMA Stream used for TX and RX DMA2 Stream 3 or 6 possible
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//DMA Stream used for TX and RX DMA2 Stream 3 or 6 possible
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@ -121,7 +121,7 @@ int sd_card_settings_save_calibration(float sens_deviation, float offset, bool a
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int ret = 0;
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int ret = 0;
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status = create_controller_folder();
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status = create_controller_folder();
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if (status)
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if (status < 0)
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return -2;
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return -2;
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get_controller_settings_path(path, sizeof(path), "offset");
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get_controller_settings_path(path, sizeof(path), "offset");
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