From 64ef7b4a3c1450a0c3c290e39ad04bdb3452ba76 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Mario=20H=C3=BCttel?= Date: Tue, 18 Aug 2020 19:30:51 +0200 Subject: [PATCH] Issue #9: Increase SDIO clock speed to 4.2 MHz --- .../fatfs/shimatta_sdio_driver/shimatta_sdio_config.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/stm-firmware/fatfs/shimatta_sdio_driver/shimatta_sdio_config.h b/stm-firmware/fatfs/shimatta_sdio_driver/shimatta_sdio_config.h index 547806c..9e81c6d 100644 --- a/stm-firmware/fatfs/shimatta_sdio_driver/shimatta_sdio_config.h +++ b/stm-firmware/fatfs/shimatta_sdio_driver/shimatta_sdio_config.h @@ -14,9 +14,9 @@ //Initial Transfer CLK (ca. 400kHz) #define INITCLK 140 //120 //Working CLK (Maximum) -#define WORKCLK 50 //0 +#define WORKCLK 8 //0 //Data Timeout in CLK Cycles -#define DTIMEOUT 0x3000 //150 +#define DTIMEOUT 0x6000 //150 //DMA Stream used for TX and RX DMA2 Stream 3 or 6 possible // Currently not used due to possible misalignment of the data buffer. //#define DMASTREAM DMA2_Stream6